Invention Application
- Patent Title: Methods for Integrated Circuit Design and Fabrication
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Application No.: US15852129Application Date: 2017-12-22
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Publication No.: US20180138042A1Publication Date: 2018-05-17
- Inventor: Tsong-Hua Ou , Ken-Hsien Hsieh , Shih-Ming Chang , Wen-Chun Huang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/027 ; H01L21/3213 ; H01L21/311 ; H01L21/321

Abstract:
The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
Public/Granted literature
- US10410863B2 Methods for integrated circuit design and fabrication Public/Granted day:2019-09-10
Information query
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