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    Distinguishable IC patterns with encoded information
    2.
    发明授权
    Distinguishable IC patterns with encoded information 有权
    具有编码信息的不可区分的IC模式

    公开(公告)号：US08806392B2

    公开(公告)日：2014-08-12

    申请号：US13692845

    申请日：2012-12-03

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shih-Ming Chang ,  Tzu-Chin Lin ,  Jen-Chieh Lo ,  Yu-Po Tang ,  Tsong-Hua Ou

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/544 ,  H01L27/0207 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

    Abstract translation: 一种设计具有填充有多个不可区分的虚拟特征的相似图案的IC设计布局的方法，以区分所有图案的方式以及如此设计的IC设计布局。 为了区分布局中的每个图案，在设计阶段期间在创建虚拟特征时，将尺寸和/或位置与某些预定平衡值的偏差编码为每个图案中的一组选定的虚拟特征。 通过识别这种编码的虚拟特征并测量由例如晶片或光掩模的SEM照片提供的图像信息的偏差，相应的图案可以位于IC布局中。 为了从给定图案更快速和更容易地识别编码的虚拟特征，可以使用一组预定的锚虚拟特征。

    Adaptive Fin Design for FinFETs
    3.
    发明申请
    Adaptive Fin Design for FinFETs 审中-公开
    FinFET的自适应鳍设计

    公开(公告)号：US20140203378A1

    公开(公告)日：2014-07-24

    申请号：US14220930

    申请日：2014-03-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tsong-Hua Ou ,  Shu-Min Chen ,  Pin-Dai Sue ,  Li-Chun Tien ,  Ru-Gun Liu

    IPC: H01L27/088

    CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0924 ,  H01L27/11803

    Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

    Abstract translation: 设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。 将标准单元放置在集成电路中并在半导体晶片上实现。

    Method of determining whether a layout is colorable
    5.
    发明授权
    Method of determining whether a layout is colorable 有权
    确定布局是否可着色的方法

    公开(公告)号：US09390223B2

    公开(公告)日：2016-07-12

    申请号：US14872338

    申请日：2015-10-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Wen-Li Cheng ,  Ming-Hui Chih ,  Chia-Ping Chiang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F1/00

    CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70433 ,  G03F7/70466

    Abstract: A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.

    Abstract translation: 确定布局是否可着色的方法包括将节点分配给布局的多边形特征。 该方法包括将节点指定为以小于最小间距分开的节点的相邻节点。 该方法包括从考虑中迭代地去除具有少于三个相邻节点的节点以识别节点布置，其中节点布置中的所有节点具有至少三个相邻节点。 该方法包括基于节点布置确定布局是否可着色。 确定布局是否可着色包括独立地评估节点布置的每个内部节点以确定节点布置的每个内部节点是否是可着色的。 该方法包括：如果节点装置的每个内部节点是可着色的，则产生用于制造半导体器件的彩色布局设计; 以及如果所述节点装置的至少一个内部节点不可着色，则修改所述布局。

    Multiple edge enabled patterning
    8.
    发明授权
    Multiple edge enabled patterning 有权
    多边缘启用图案化

    公开(公告)号：US09287125B2

    公开(公告)日：2016-03-15

    申请号：US14280757

    申请日：2014-05-19

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ming-Feng Shieh ,  Ya Hui Chang ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Burn Jeng Lin

    IPC: G03F1/42 ,  G03F9/00 ,  H01L21/033 ,  H01L23/544

    CPC classification number: H01L23/544 ,  G03F1/42 ,  G03F9/7076 ,  H01L21/0337 ,  H01L21/0338 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

    Abstract translation: 提供具有多个次分辨率元素的对准标记。 子分辨率元素各自具有小于可由对准过程中使用的对准信号检测的最小分辨率的维度。 还提供了其上形成有第一，第二和第三图案的半导体晶片。 第一和第二图案在第一方向上延伸，并且第三图案沿垂直于第一方向的第二方向延伸。 第二图案与第一图案分离在第二方向上测量的第一距离。 第三图案与第一图案分离在第一方向上测量的第二距离。 第三图案与第二图案分离在第一方向上测量的第三距离。 第一距离近似等于第三距离。 第二距离小于第一距离的两倍。

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