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    Contour alignment system
    3.
    发明授权
    Contour alignment system 有权
    轮廓对齐系统

    公开(公告)号：US08954899B2

    公开(公告)日：2015-02-10

    申请号：US13645256

    申请日：2012-10-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Chieh Wu ,  Tzu-Chin Lin ,  Hung-Ting Lu ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F7/00

    CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/00

    Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.

    Abstract translation: 本公开描述了校准轮廓的方法。 该方法包括设计锚定图案，在基板上印刷锚图案，在基板上收集印刷的锚图案的扫描电子显微镜（SEM）数据，其中SEM数据包括印刷的锚图案在基板上的SEM图像， 将印刷的锚定图案的SEM图像转印到印刷锚定图案的SEM轮廓上，分析印刷的锚图案的SEM轮廓，并对准锚定图案的SEM轮廓以形成校准的SEM轮廓。

    ENVIRONMENTAL-SURROUNDING-AWARE OPC
    7.
    发明申请
    ENVIRONMENTAL-SURROUNDING-AWARE OPC 有权
    环境环保型OPC

    公开(公告)号：US20170053055A1

    公开(公告)日：2017-02-23

    申请号：US14831926

    申请日：2015-08-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Wen-Li Cheng ,  Ming-Hui Chih ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G06F17/50

    CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F1/72

    Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

    Abstract translation: 本公开提供了一种执行光学邻近校正（OPC）的方法。 收到集成电路（IC）设计布局。 设计布局包含多个IC布局图案。 多个IC布局图案中的两个或更多个被分组在一起。 解剖分组的IC布局模式，或为分组的IC布局模式设置目标点。 此后，基于分组的IC布局模式执行OPC处理。

    METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION
    8.
    发明申请
    METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION 有权
    集成电路设计与制造方法

    公开(公告)号：US20160293422A1

    公开(公告)日：2016-10-06

    申请号：US15174131

    申请日：2016-06-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Wen-Chun Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

    IPC: H01L21/033

    CPC classification number: H01L21/0338 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139

    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

    Abstract translation: 本公开提供了在半导体衬底上图案化靶材料层的方法。 该方法包括以下步骤：使用第一子布局在目标材料层上形成间隔物特征，并使用第二子布局进行光刻图案化处理以形成第一特征。 第一特征的一部分在间隔物特征上延伸。 该方法还包括以下步骤：移除在间隔物特征上延伸的第一特征的部分并去除间隔物特征。 本文还提供了其它方法和相关的图案化半导体晶片。

    Enhanced EUV lithography system
    10.
    发明授权
    Enhanced EUV lithography system 有权

    公开(公告)号：US09395618B2

    公开(公告)日：2016-07-19

    申请号：US14807999

    申请日：2015-07-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ching-Hsu Chang ,  Nian-Fuh Cheng ,  Chih-Shiang Chou ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G03F1/22 ,  G03F1/70 ,  G03F7/20

    CPC classification number: G03F1/22 ,  G03F1/70 ,  G03F7/70066 ,  G03F7/70283 ,  G03F7/70433

    Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.

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