Invention Application
- Patent Title: EMBEDDED ETCH RATE REFERENCE LAYER FOR ENHANCED ETCH TIME PRECISION
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Application No.: US16145143Application Date: 2018-09-27
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Publication No.: US20200105628A1Publication Date: 2020-04-02
- Inventor: Yann Mignot , Alan Thomas , Daniel Sanders , Dario Goldfarb , Nelson Felix , Chi-Chun Liu , John Arnold
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/02 ; H01L21/311
Abstract:
An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.
Public/Granted literature
- US10748823B2 Embedded etch rate reference layer for enhanced etch time precision Public/Granted day:2020-08-18
Information query
IPC分类:
