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    EMBEDDED MRAM DEVICE FORMATION WITH SELF-ALIGNED DIELECTRIC CAP
    2.
    发明申请
    EMBEDDED MRAM DEVICE FORMATION WITH SELF-ALIGNED DIELECTRIC CAP 有权

    公开(公告)号：US20210091301A1

    公开(公告)日：2021-03-25

    申请号：US16578729

    申请日：2019-09-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： John Arnold ,  Dominik Metzler ,  Ashim Dutta ,  Donald Canaperi

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

    Self-Aligned Top Via Formation at Line Ends
    4.
    发明申请
    Self-Aligned Top Via Formation at Line Ends 有权

    公开(公告)号：US20210125865A1

    公开(公告)日：2021-04-29

    申请号：US16664830

    申请日：2019-10-26

    Applicant: International Business Machines Corporation

    Inventor： Ashim Dutta ,  John Arnold ,  Dominik Metzler

    IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532

    Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.

    Controlled Ion Beam Etch of MTJ
    6.
    发明申请
    Controlled Ion Beam Etch of MTJ 有权

    公开(公告)号：US20210091306A1

    公开(公告)日：2021-03-25

    申请号：US16582762

    申请日：2019-09-25

    Applicant: International Business Machines Corporation

    Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lijuan Zou ,  John Arnold

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

    Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

    PLACING TOP VIAS AT LINE ENDS BY SELECTIVE GROWTH OF VIA MASK FROM LINE CUT DIELECTRIC
    10.
    发明申请
    PLACING TOP VIAS AT LINE ENDS BY SELECTIVE GROWTH OF VIA MASK FROM LINE CUT DIELECTRIC 有权

    公开(公告)号：US20210082807A1

    公开(公告)日：2021-03-18

    申请号：US16574447

    申请日：2019-09-18

    Applicant: International Business Machines Corporation

    Inventor： Ashim DUTTA ,  Ekmini Anuja De Silva ,  Dominik METZLER ,  John Arnold

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

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