公开(公告)号：US10748823B2

公开(公告)日：2020-08-18

申请号：US16145143

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Alan Thomas ,  Daniel Sanders ,  Dario Goldfarb ,  Nelson Felix ,  Chi-Chun Liu ,  John Arnold

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/02 ,  H01L21/311

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

公开(公告)号：US20200105628A1

公开(公告)日：2020-04-02

申请号：US16145143

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Alan Thomas ,  Daniel Sanders ,  Dario Goldfarb ,  Nelson Felix ,  Chi-Chun Liu ,  John Arnold

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/311

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

公开(公告)号：US10832971B2

公开(公告)日：2020-11-10

申请号：US16117258

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Rajasekhar Venigalla ,  Ravikumar Ramachandran ,  Albert Chu ,  Alan Thomas ,  Kafai Lai

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/308

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.