公开(公告)号：US20240332182A1

公开(公告)日：2024-10-03

申请号：US18129048

申请日：2023-03-30

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Shahab Siddiqui ,  Chanro Park ,  Ruilong Xie

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A MOSFET includes a semiconductor substrate that has a frontside and a backside; a metal gate at the frontside of the substrate; a first source/drain structure at the frontside of the substrate, adjacent to the metal gate in a first direction; and a first source/drain contact at the frontside of the first source/drain structure. Also included are a backside power rail at the backside of the substrate; and a recessed via that connects the first source/drain contact through the substrate to the backside power rail. The recessed via is adjacent to the first source/drain structure in a direction perpendicular to the first direction. A dielectric cap covers a frontside of the first source/drain contact. A gate contact is disposed at a frontside of the dielectric cap. The gate contact at least partly overlies the first source/drain contact.

公开(公告)号：US20240312839A1

公开(公告)日：2024-09-19

申请号：US18122680

申请日：2023-03-16

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Koichi Motoyama ,  Yann Mignot

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a lower level via that is fully aligned to an upper level metal line. The lower level via is elongated along a lower level metal line direction and partially recessed.

公开(公告)号：US20240162087A1

公开(公告)日：2024-05-16

申请号：US17985138

申请日：2022-11-10

Applicant: International Business Machines Corporation

Inventor： Xiaoming Yang ,  Yann Mignot ,  SOMNATH GHOSH ,  Daniel Charles Edelstein

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/76877 ,  H01L21/0272 ,  H01L21/0332 ,  H01L21/76802

Abstract: A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

公开(公告)号：US11670580B2

公开(公告)日：2023-06-06

申请号：US17461096

申请日：2021-08-30

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Hsueh-Chung Chen ,  Junli Wang ,  Mary Claire Silvestre ,  Chi-Chun Liu

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/90

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

公开(公告)号：US20230145135A1

公开(公告)日：2023-05-11

申请号：US17520812

申请日：2021-11-08

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Su Chen Fan ,  Jing Guo ,  Lijuan Zou

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT

公开(公告)号：US20230091229A1

公开(公告)日：2023-03-23

申请号：US17479794

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Ruilong Xie ,  Yann Mignot ,  Tsung-Sheng Kang ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor structure comprises at least one vertical fin, an epitaxial layer adjacent a bottom portion of the at least one vertical fin, wherein the epitaxial layer comprises a plurality of different heights, and a contact structure disposed on the epitaxial layer. The contact structure is disposed on respective surfaces of the epitaxial layer at the plurality of different heights. The epitaxial layer comprises a bottom source/drain region of at least one vertical transport field-effect transistor.

公开(公告)号：US20230063908A1

公开(公告)日：2023-03-02

申请号：US17461096

申请日：2021-08-30

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Hsueh-Chung Chen ,  Junli Wang ,  Mary Claire Silvestre ,  Chi-Chun LIU

IPC: H01L23/522 ,  H01L49/02

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

公开(公告)号：US11501969B2

公开(公告)日：2022-11-15

申请号：US16253429

申请日：2019-01-22

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Chi-Chun Liu

IPC: H01L21/033

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

公开(公告)号：US20220005762A1

公开(公告)日：2022-01-06

申请号：US17480824

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  James J. Kelly ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Hsueh-Chung Chen ,  Daniel J. Vincent

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

公开(公告)号：US11037822B2

公开(公告)日：2021-06-15

申请号：US16406447

申请日：2019-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Joe Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/321

Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.