发明授权
US4804560A Method of selectively depositing tungsten upon a semiconductor substrate
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在半导体衬底上选择性地沉积钨的方法
- 专利标题: Method of selectively depositing tungsten upon a semiconductor substrate
- 专利标题(中): 在半导体衬底上选择性地沉积钨的方法
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申请号: US026900申请日: 1987-03-17
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公开(公告)号: US4804560A公开(公告)日: 1989-02-14
- 发明人: Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
- 申请人: Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
- 申请人地址: JPX Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX61-58753 19860317
- 主分类号: H01L21/205
- IPC分类号: H01L21/205 ; C23C16/04 ; C23C16/14 ; H01L21/28 ; H01L21/285 ; H01L21/3205 ; H01L21/768 ; B05D5/12 ; C23C16/00
摘要:
A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface. Aluminum film is deposited on the flat surface and patterned by lithography. The flat aluminum deposition allows fabrication of accurate and reliable wirings and facilitates production of VLSI of sub-micron order.
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