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公开(公告)号:US4804560A
公开(公告)日:1989-02-14
申请号:US026900
申请日:1987-03-17
申请人: Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
发明人: Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
IPC分类号: H01L21/205 , C23C16/04 , C23C16/14 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , B05D5/12 , C23C16/00
CPC分类号: H01L21/28562 , H01L21/32051 , H01L21/76879
摘要: A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface. Aluminum film is deposited on the flat surface and patterned by lithography. The flat aluminum deposition allows fabrication of accurate and reliable wirings and facilitates production of VLSI of sub-micron order.
摘要翻译: 一种在硅半导体衬底上选择性地沉积钨的方法。 硅衬底涂覆有被图案化以提供用于形成电极或布线的开口的PSG或SiO 2的掩模膜。 在开口中的基板的一部分上,通过CVD法从含有WF6和H2的气体混合物的大气层沉积厚度约为2000的钨层。 在该处理中,钨核沉积在掩模膜的表面上也是如此。 在这种核形成膜之前,中断沉积处理,并且将H 2气体进料到CVD装置中以产生HF,其蚀刻掩模膜的表面,因此除去钨原子。 沉积和去除步骤重复几次,直到沉积的钨的高度和掩模膜的厚度基本上等于呈现平坦表面。 铝膜沉积在平坦表面上并通过光刻图案化。 扁平铝沉积允许制造准确可靠的布线,并有助于生产亚微米级VLSI。