发明授权
US6122724A Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation 有权
中央处理单元具有32位长度的指令队列,在一个指令提取操作中获取16位固定长度的两个指令

Central processing unit having instruction queue of 32-bit length
fetching two instructions of 16-bit fixed length in one instruction
fetch operation
摘要:
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
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