发明授权
- 专利标题: Semiconductor integrated circuit device
- 专利标题(中): 半导体集成电路器件
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申请号: US10322594申请日: 2002-12-19
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公开(公告)号: US06879188B2公开(公告)日: 2005-04-12
- 发明人: Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
- 申请人: Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
- 申请人地址: JP Tokyo JP Tokyo
- 专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人地址: JP Tokyo JP Tokyo
- 代理机构: Antonelli, Terry, Stout & Kraus, LLP
- 优先权: JP11-147664 19990527
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/06 ; G06F1/32 ; H01L21/82 ; H01L21/822 ; H01L27/04 ; H03L7/07 ; H03L7/081 ; H03L7/099 ; H03B19/00
摘要:
A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.
公开/授权文献
- US20030098730A1 Semiconductor integrated circuit device 公开/授权日:2003-05-29
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