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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06879188B2

    公开(公告)日：2005-04-12

    申请号：US10322594

    申请日：2002-12-19

    申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/32 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H03B19/00

    CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

    摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

    摘要翻译： 一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的 。 时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现， 时钟建立时间很小，例如2-3个周期。 由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗 而不会影响时钟振荡器的响应。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06515519B1

    公开(公告)日：2003-02-04

    申请号：US09580646

    申请日：2000-05-30

    申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    IPC分类号： H03B1900

    CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

    摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

    摘要翻译： 来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。 输入时钟信号ck11由分频器DIV1分频为期望值。 输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。 锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

    Timing-control circuit device and clock distribution system
    3.
    发明授权
    Timing-control circuit device and clock distribution system 有权
    定时控制电路设备和时钟分配系统

    公开(公告)号：US06300807B1

    公开(公告)日：2001-10-09

    申请号：US09388438

    申请日：1999-09-02

    申请人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

    发明人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

    IPC分类号： H03L706

    CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/135 ,  H04L7/0037

    摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.

    摘要翻译： 使用同步镜延迟电路的定时控制电路装置即使在负载变化时也保持时钟信号同步。 参考时钟信号（clkin 11）被输入到定时控制电路（SMDF 14），用于产生内部时钟（dclk12），然后通过缓冲器（BUF 15）产生外部时钟（clkout 13）。 外部时钟信号被反馈到定时控制电路（SMDF14），用于产生内部时钟信号，以使外部时钟信号与参考时钟信号同相。 定时控制电路设置有用于检测内部时钟信号和外部时钟信号之间的相位差的电路（FDA 21，MCC 22）以及用于控制延迟时间的延迟电路（DCL 24），因此 延迟电路（DCL24）可以根据检测到的相位差来改变延迟时间。

    X-ray analyzer and mapping method for an X-ray analysis
    6.
    发明授权
    X-ray analyzer and mapping method for an X-ray analysis 有权
    X射线分析仪和X线分析的绘图方法

    公开(公告)号：US08705698B2

    公开(公告)日：2014-04-22

    申请号：US13027881

    申请日：2011-02-15

    申请人： Hiroshi Matsumura ,  Kiyoshi Hasegawa

    发明人： Hiroshi Matsumura ,  Kiyoshi Hasegawa

    IPC分类号： H05G1/62 ,  G01N23/201 ,  G06K9/78 ,  G06K9/82

    CPC分类号： G01N23/223 ,  G01N2223/076 ,  G06T7/001 ,  G06T2207/10061 ,  G06T2207/10121 ,  G06T2207/30148

    摘要： Provided are an X-ray analyzer and a mapping method for an X-ray analysis which, in a inspection for a harmful substance contained in, for example, a material or a composite electronic component, enable determination as to whether a sample is normal or abnormal to be performed visually based on an image obtained by the X-ray mapping analysis. In the X-ray analyzer, an X-ray mapping image of a sample which is confirmed to be normal in advance is obtained as a reference mapping image. A mapping analysis is performed on a inspection sample. A difference from the reference mapping image is obtained for each pixel, to thereby display a difference mapping image. A region in which the amount of specific element is larger than a reference amount is displayed with high brightness, and hence an abnormal portion may be easily found.

    摘要翻译： 提供了一种X射线分析仪和用于X射线分析的映射方法，其在包含在例如材料或复合电子部件中的有害物质的检查中能够确定样品是正常还是 基于通过X射线映射分析获得的图像，可视化地进行异常。 在X射线分析装置中，作为基准对照图像，获得确认为正常的样本的X射线映射图像。 对检查样品进行映射分析。 对于每个像素获得与参考映射图像的差异，从而显示差异映射图像。 特定元素的量大于基准量的区域以高亮度显示，因此可能容易发现异常部分。

    SUBSTRATE FOR MOUNTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING SAME
    7.
    发明申请
    SUBSTRATE FOR MOUNTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING SAME 有权
    用于安装半导体芯片的基板及其制造方法

    公开(公告)号：US20120234584A1

    公开(公告)日：2012-09-20

    申请号：US13394688

    申请日：2010-09-06

    申请人： Yoshinori Ejiri ,  Kiyoshi Hasegawa ,  Takehisa Sakurai ,  Yoshiaki Tsubomatsu

    发明人： Yoshinori Ejiri ,  Kiyoshi Hasegawa ,  Takehisa Sakurai ,  Yoshiaki Tsubomatsu

    IPC分类号： H05K1/16 ,  H05K1/09

    CPC分类号： H05K3/244 ,  H01L21/4857 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/062 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/4652 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

    摘要： It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings. The method for producing a substrate for mounting a semiconductor chip according to the invention comprises a resist-forming step in which a resist is formed on the first copper layer of a stack comprising an inner board with an inner layer circuit on the surface and a first copper layer formed on the inner board separated by an insulating layer at the sections other than those that are to constitute a conductor circuit, a conductor circuit-forming step in which a second copper layer is formed by electrolytic copper plating on the first copper layer to obtain a conductor circuit, a nickel layer-forming step in which a nickel layer is formed by electrolytic nickel plating on at least part of the conductor circuit, a resist removal step in which the resist is removed, an etching step in which the first copper layer is removed by etching, and a gold layer-forming step in which a gold layer is formed by electroless gold plating on at least part of the conductor circuit.

    摘要翻译： 本发明的目的是提供一种用于制造用于安装半导体芯片的基板的方法，即使在形成精细间距布线时也能够减少桥接并且能够获得优异的引线接合性和焊接连接可靠性。 根据本发明的用于制造用于安装半导体芯片的基板的方法包括抗蚀剂形成步骤，其中在包括在内表层电路的内板上的第一铜层上形成抗蚀剂，并且第一 铜层，其形成在内板上，除了构成导体电路的部分之外的绝缘层分隔开;导体电路形成步骤，其中通过在第一铜层上的电解铜电镀形成第二铜层， 获得导体电路，镍层形成步骤，其中在导体电路的至少一部分上通过电解镀镍形成镍层，去除抗蚀剂的抗蚀剂去除步骤，其中第一铜 通过蚀刻去除层，以及金层形成步骤，其中在导体电路的至少一部分上通过无电镀金形成金层。

    Surface finishing apparatus and related method
    9.
    发明授权
    Surface finishing apparatus and related method 有权
    表面处理装置及相关方法

    公开(公告)号：US07794306B2

    公开(公告)日：2010-09-14

    申请号：US10772429

    申请日：2004-02-06

    申请人： Tomohiro Kondo ,  Masahiko Iizumi ,  Masahiro Omata ,  Kiyoshi Hasegawa ,  Takashi Ogino ,  Takafumi Watanabe ,  Yoshiyuki Chida ,  Yasushi Matsushita ,  Kazuo Takeda

    发明人： Tomohiro Kondo ,  Masahiko Iizumi ,  Masahiro Omata ,  Kiyoshi Hasegawa ,  Takashi Ogino ,  Takafumi Watanabe ,  Yoshiyuki Chida ,  Yasushi Matsushita ,  Kazuo Takeda

    IPC分类号： B24B1/30

    CPC分类号： B24B49/16 ,  B24B5/42 ,  B24B19/12 ,  B24B21/00

    摘要： An apparatus and method for surface finishing a workpiece is disclosed as including a workpiece supporting mechanism supporting a workpiece having a target shaped periphery with a given width to be surface finished and a tool holder holding a surface finish tool in abutting contact with the target shaped periphery of the workpiece. A pressure applying mechanism is operative to apply a pressure force to the surface finish tool through the tool holder to cause the surface finish tool to be held in pressured contact with the target shaped periphery, with the pressure force exhibiting a given distribution pattern depending upon an axial direction of the workpiece. A drive mechanism rotates the workpiece to allow the surface finish tool to surface finish the target shaped periphery into a given geometrical profile, variably contoured along an axis of the workpiece depending on the given pressure distribution pattern.

    摘要翻译： 公开了一种用于表面处理工件的装置和方法，包括：工件支撑机构，其支撑具有待表面加工的给定宽度的目标形状周边的工件;以及保持表面加工工具以与目标形状周边抵接的工具架 的工件。 压力施加机构可操作以通过工具保持器向表面加工工具施加压力，以使表面精加工工具与目标形状的周边保持压力接触，其中压力显示给定的分布图案，这取决于 工件的轴向。 驱动机构使工件旋转以允许表面光洁度工具将目标形状的周边表面光洁成给定的几何轮廓，根据给定的压力分布图案沿着工件的轴线可变地轮廓。