Invention Grant
US08652907B2 Integrating transistors with different poly-silicon heights on the same die
有权
将晶体管与不同的多晶硅高度集成在同一芯片上
- Patent Title: Integrating transistors with different poly-silicon heights on the same die
- Patent Title (中): 将晶体管与不同的多晶硅高度集成在同一芯片上
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Application No.: US13071385Application Date: 2011-03-24
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Publication No.: US08652907B2Publication Date: 2014-02-18
- Inventor: Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
- Applicant: Chuan Lin , Hidehiko Shiraiwa , Bradley Marc Davis , Lei Xue , Simon S. Chan , Kenichi Ohtsuka , Angela T. Hui , Scott Allan Bell
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/8234
Abstract:
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
Public/Granted literature
- US20120241871A1 INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE Public/Granted day:2012-09-27
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