公开(公告)号：US08809936B2

公开(公告)日：2014-08-19

申请号：US11461428

申请日：2006-07-31

Applicant: Lei Xue ,  Rinji Sugino ,  YouSeok Suh ,  Hidehiko Shiraiwa ,  Meng Ding ,  Shenqing Fang ,  Joong Jeon

Inventor： Lei Xue ,  Rinji Sugino ,  YouSeok Suh ,  Hidehiko Shiraiwa ,  Meng Ding ,  Shenqing Fang ,  Joong Jeon

IPC: H01L29/788

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Abstract translation: 提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。

公开(公告)号：US08279674B2

公开(公告)日：2012-10-02

申请号：US12824352

申请日：2010-06-28

Applicant: Richard Fastow ,  Hagop Nazarian ,  Lei Xue

Inventor： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC: G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

Abstract: Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

Abstract translation: 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20120202355A1

公开(公告)日：2012-08-09

申请号：US13022517

申请日：2011-02-07

Applicant: Rinji Sugino ,  Bradley Marc Davis ,  Lei Xue ,  Kenichi Ohtsuka

Inventor： Rinji Sugino ,  Bradley Marc Davis ,  Lei Xue ,  Kenichi Ohtsuka

IPC: H01L21/465 ,  H01L21/46

CPC classification number: H01L21/02271 ,  C23C16/045 ,  C23C16/44 ,  C23C16/56 ,  H01L21/02164 ,  H01L27/11568

Abstract: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.

Abstract translation: 提供了半导体器件制造方法。 本发明的实施例涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片，以产生在所有产品晶片上基本均匀的侧壁层厚度变化。 至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面，其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。 此外，在间歇式化学气相沉积（CVD）系统中，至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。 在另一个实施例中，至少一个图案化虚设晶片可以放置在CVD系统的排气附近。 此外，图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。

公开(公告)号：US20090042378A1

公开(公告)日：2009-02-12

申请号：US11835538

申请日：2007-08-08

Applicant: Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T. Chang ,  Huaqiang Wu

Inventor： Ning Cheng ,  Calvin Gabriel ,  Angela Hui ,  Lei Xue ,  Harpreet Kaur Sachar ,  Phillip Lawrence Jones ,  Hiro Kinoshita ,  K.T. Chang ,  Huaqiang Wu

IPC: H01L21/22

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Abstract translation: 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。 与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

公开(公告)号：US20090039405A1

公开(公告)日：2009-02-12

申请号：US11835542

申请日：2007-08-08

Applicant: Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

Inventor： Ning Cheng ,  K.T. Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Abstract translation: 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US07416940B1

公开(公告)日：2008-08-26

申请号：US11418352

申请日：2006-05-03

Applicant: Satoshi Torii ,  Hidehiko Shiraiwa ,  Youseok Suh ,  Lei Xue

Inventor： Satoshi Torii ,  Hidehiko Shiraiwa ,  Youseok Suh ,  Lei Xue

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.

Abstract translation: 提供了制造闪速存储器件的方法。 一种方法包括形成覆盖衬底的多个栅叠层。 每个栅极堆叠包括电荷捕获层和控制栅极。 控制栅极是离基板的第一距离。 相邻的门堆叠是第二个距离。 沉积电池间隔物材料层并被蚀刻以形成围绕每个栅极叠层的侧壁的间隔物。 在第一栅极堆叠和最后一个栅极堆叠附近形成源极/漏极杂质掺杂区域。 第一距离和第二距离使得当在读取操作期间将电压施加到栅极堆叠时，在栅极堆叠的控制栅极和衬底之间产生边缘场，并且足以将一部分 栅极堆叠和相邻栅极堆叠之间的衬底。

公开(公告)号：US20080083946A1

公开(公告)日：2008-04-10

申请号：US11539984

申请日：2006-10-10

Applicant: Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

Inventor： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

IPC: H01L29/792 ,  H01L21/8238

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11568

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.

Abstract translation: 提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

公开(公告)号：US20080023750A1

公开(公告)日：2008-01-31

申请号：US11461428

申请日：2006-07-31

Applicant: Lei Xue ,  Rinji Sugino ,  YouSeok Suh ,  Hidehiko Shiraiwa ,  Meng Ding ,  Shenqing Fang ,  Joong Jeon

Inventor： Lei Xue ,  Rinji Sugino ,  YouSeok Suh ,  Hidehiko Shiraiwa ,  Meng Ding ,  Shenqing Fang ,  Joong Jeon

IPC: H01L29/788

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Abstract translation: 提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。

公开(公告)号：US20080012060A1

公开(公告)日：2008-01-17

申请号：US11458046

申请日：2006-07-17

Applicant: Meng Ding ,  Amol Ramesh Joshi ,  Lei Xue ,  Takashi Orimoto ,  Kuo-Tung Chang

Inventor： Meng Ding ,  Amol Ramesh Joshi ,  Lei Xue ,  Takashi Orimoto ,  Kuo-Tung Chang

IPC: H01L29/76

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract translation: 提供一种存储单元系统，在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成中间层，并与中间层形成第二绝缘体层。

公开(公告)号：US07059876B2

公开(公告)日：2006-06-13

申请号：US10951501

申请日：2004-09-27

Applicant: Chi Zhang ,  Ya-Lei Xue

Inventor： Chi Zhang ,  Ya-Lei Xue

IPC: H01R13/44

CPC classification number: H01R43/205 ,  Y10S439/94

Abstract: An electrical connector assembly includes a right-angle connector (1) and a pick-up device (2) assembled to the connector (1) to provide a vacuum suction surface. The right-angle connector (1) includes a dielectric housing (10) with a mating portion (11), a mounting face (120), and a pair of locking portions (121). The pick-up device (2) is assembled to the connector (1) in a direction parallel to mounting face (120) and comprises a rectangular base (20) having a substantially planar upper surface (200) and an opposite lower surface (201), and a pair of retaining portions (21) depending down from the lower surface (201) and engaged with the locking portions (121) of the connector (1).

Abstract translation: 电连接器组件包括直角连接器（1）和组装到连接器（1）上以提供真空吸附表面的拾取装置（2）。 直角连接器（1）包括具有配合部分（11），安装面（120）和一对锁定部分（121）的绝缘壳体（10）。 拾取装置（2）在与安装面（120）平行的方向上组装到连接器（1），并且包括具有基本平坦的上表面（200）和相对的下表面（201）的矩形基座（20） ）和从下表面（201）向下倾斜并与连接器（1）的锁定部分（121）接合的一对保持部分（21）。