Invention Grant
US09105497B2 Methods of forming gate structures for transistor devices for CMOS applications
有权
为CMOS应用形成晶体管器件的栅极结构的方法
- Patent Title: Methods of forming gate structures for transistor devices for CMOS applications
- Patent Title (中): 为CMOS应用形成晶体管器件的栅极结构的方法
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Application No.: US14017485Application Date: 2013-09-04
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Publication No.: US09105497B2Publication Date: 2015-08-11
- Inventor: Zhendong Hong , Susie Tzeng , Amol Joshi , Ashish Bodke , Divya Pisharoty , Usha Raghuram , Olov Karlsson , Kisik Choi , Salil Mujumdar , Paul R. Besser , Jinping Liu , Hoon Kim
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L27/092 ; H01L29/51 ; H01L29/66 ; H01L21/8238

Abstract:
One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.
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