公开(公告)号：US20150303057A1

公开(公告)日：2015-10-22

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US20150061027A1

公开(公告)日：2015-03-05

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

公开(公告)号：US09362283B2

公开(公告)日：2016-06-07

申请号：US14793005

申请日：2015-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract translation: 集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料， 位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层 并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。

公开(公告)号：US09196475B2

公开(公告)日：2015-11-24

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US09105497B2

公开(公告)日：2015-08-11

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。