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    Tantalum carbide metal gate stack for mid-gap work function applications
    2.
    发明申请
    Tantalum carbide metal gate stack for mid-gap work function applications 审中-公开
    用于中间隙功能应用的钽硬质合金金属栅极叠层

    公开(公告)号：US20160093711A1

    公开(公告)日：2016-03-31

    申请号：US14315079

    申请日：2014-06-25

    Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    Inventor： Zhendong Hong ,  Paul Besser ,  Kisik Choi ,  Amol Joshi ,  Olov Karlsson ,  Susie Tzeng

    IPC: H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

    Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

    Abstract translation: 具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。 碳化钽（TaC）具有对厚度不敏感的中间间隙功能。 可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。 可以添加Al来调节阈值电压。

    Methods of forming gate structures for transistor devices for CMOS applications
    3.
    发明授权
    Methods of forming gate structures for transistor devices for CMOS applications 有权
    为CMOS应用形成晶体管器件的栅极结构的方法

    公开(公告)号：US09105497B2

    公开(公告)日：2015-08-11

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS
    5.
    发明申请
    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS 审中-公开
    用于在整体电路制造中沉积锗永磁体的氧化铝层的方法

    公开(公告)号：US20150093914A1

    公开(公告)日：2015-04-02

    申请号：US14044514

    申请日：2013-10-02

    Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

    Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

    IPC: H01L21/02

    CPC classification number: H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.

    Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括形成在其上的GeO x层的锗基半导体衬底，并将半导体衬底暴露于第一和第二原子层沉积（ALD）工艺。 第一ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第一含氧前体的第二气态前体。 第二ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第二含氧前体的第二气态前体。

    Metal-insulator-semiconductor (MIS) contact with controlled defect density
    6.
    发明申请
    Metal-insulator-semiconductor (MIS) contact with controlled defect density 审中-公开
    金属 - 绝缘体 - 半导体（MIS）接触具有受控的缺陷密度

    公开(公告)号：US20150380309A1

    公开(公告)日：2015-12-31

    申请号：US14315718

    申请日：2014-06-26

    Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    Inventor： Salil Mujumdar ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  Bin Yang

    IPC: H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/517 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/285 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

    Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体（MIS）触点包括通过原子层沉积（ALD）沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力，同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数，例如缩短的氧化剂脉冲，使用较少反应性的氧化剂例如水，在沉积期间加热衬底，在沉积之前对自然氧化物进行TMA“清洁”，以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力，冷却的氧化剂和金属前体的缩短的脉冲。

    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    8.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
    用于CMOS应用和结果产品的晶体管器件的门结构的方法

    公开(公告)号：US20150061027A1

    公开(公告)日：2015-03-05

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

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