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    Metal gate structure for midgap semiconductor device and method of making same
    1.
    发明授权
    Metal gate structure for midgap semiconductor device and method of making same 有权
    中间半导体器件的金属栅极结构及其制造方法

    公开(公告)号：US09496143B2

    公开(公告)日：2016-11-15

    申请号：US13670251

    申请日：2012-11-06

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L21/02 ,  H01L21/8222 ,  H01L21/28 ,  H01L29/49

    CPC classification number: H01L21/28088 ,  H01L29/4966

    Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

    Abstract translation: 通过包括相对较厚的TiN的退火层来支配并将整个功函数从PFET的整个功能转移到底部，从而产生用于在NFET和PFET之间进行阈值电压控制的中隙工作功能的基于PFET的半导体栅极结构。 该结构具有覆盖有高k电介质层，退火TiN层，未退火TiN层，未退火TiN上的薄势垒和薄势垒上的n型金属的PFET基极。

    Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices
    6.
    发明授权
    Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices 有权
    为基于CMOS的集成电路产品形成栅极结构的方法和所得到的器件

    公开(公告)号：US09165928B2

    公开(公告)日：2015-10-20

    申请号：US13918569

    申请日：2013-06-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Kisik Choi

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/42356 ,  H01L29/4975

    Abstract: One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.

    Abstract translation: 本文公开的一种说明性方法包括从相同材料形成用于NMOS和PMOS器件的栅极绝缘层和第一金属层，仅选择性地形成用于PMOS器件的第一金属层，以及在NMOS和PMOS栅极内形成不同形状的金属硅化物区域 空腔 本文公开的新型集成电路产品包括具有NMOS栅极绝缘层的NMOS晶体管，具有大致矩形横截面构造的NMOS金属硅化物和位于NMOS金属硅化物区域上的NMOS金属层。 该产品还包括具有相同栅极绝缘材料的PMOS晶体管，第一PMOS金属和PMOS金属硅化物区域，其中NMOS和PMOS金属硅化物区域由相同的金属硅化物组成。

    Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices
    9.
    发明授权
    Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices 有权
    为基于CMOS的集成电路产品形成栅极结构的方法和所得到的器件

    公开(公告)号：US09024388B2

    公开(公告)日：2015-05-05

    申请号：US13919676

    申请日：2013-06-17

    Applicant: GlobalFoundries Inc.

    Inventor： Kisik Choi ,  Ruilong Xie

    IPC: H01L29/43 ,  H01L29/45 ,  H01L29/772 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/823443 ,  H01L21/28008 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.

    Abstract translation: 本文公开的一种说明性方法包括通过从相同的材料形成栅极绝缘层和用于器件的第一金属层并且仅在第一金属层上选择性地形成金属硅化物材料层来形成用于NMOS晶体管和PMOS晶体管的替代栅极结构 对于NMOS器件，但不在PMOS器件上。 本文公开的新颖的集成电路产品的一个示例包括NMOS器件和PMOS器件，其中栅极绝缘层和器件的栅极结构的第一金属层由相同的材料制成，NMOS器件的栅极结构包括 位于所述NMOS器件的所述第一金属层上的金属硅化物材料，以及位于所述NMOS器件的所述金属硅化物材料上以及所述PMOS器件的所述第一金属层上的第二金属层。

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