Invention Grant
- Patent Title: A-priori-probability-phase-estimation for digital phase-locked loops
- Patent Title (中): 数字锁相环的先验概率相位估计
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Application No.: US14490115Application Date: 2014-09-18
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Publication No.: US09231602B1Publication Date: 2016-01-05
- Inventor: Elan Banin , Rotem Banin , Ofir Degani , Ran Shimon , Ashoke Ravi
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Eschweiler & Associates, LLC
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/08 ; G04F10/00

Abstract:
A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.
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