Invention Grant
US09298643B2 Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty
有权
对于缓存在一级数据高速缓存和行中的二级组合高速缓存/ SRAM的DMA写入性能和功率改进是有效和脏的
- Patent Title: Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty
- Patent Title (中): 对于缓存在一级数据高速缓存和行中的二级组合高速缓存/ SRAM的DMA写入性能和功率改进是有效和脏的
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Application No.: US14728541Application Date: 2015-06-02
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Publication No.: US09298643B2Publication Date: 2016-03-29
- Inventor: Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F7/483 ; G06F9/30 ; H03M13/35 ; H03M13/29 ; G06F11/10 ; G06F13/16 ; G06F13/18 ; H03K19/00 ; G06F1/32 ; H03K21/00 ; G06F12/02 ; G06F12/12 ; G06F12/08 ; G06F13/364
Abstract:
This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.
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