Invention Grant
- Patent Title: Device packaging with substrates having embedded lines and metal defined pads
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Application No.: US14798395Application Date: 2015-07-13
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Publication No.: US09355952B2Publication Date: 2016-05-31
- Inventor: Mark S. Hlad , Islam A. Salama , Mihir K. Roy , Tao Wu , Yueli Liu , Kyu Oh Lee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/40 ; H01L21/44 ; H01L23/498 ; H01L21/48 ; H01L23/00 ; H01L23/50 ; H05K1/11 ; H05K3/10 ; H05K3/42 ; H01L21/56 ; H05K3/34
Abstract:
Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
Public/Granted literature
- US20150318238A1 DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS Public/Granted day:2015-11-05
Information query
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