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    Methods of forming a package substrate
    1.
    发明授权
    Methods of forming a package substrate 有权

    公开(公告)号：US11443970B2

    公开(公告)日：2022-09-13

    申请号：US16803361

    申请日：2020-02-27

    Applicant: Intel Corporation

    Inventor： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

    IPC: H01L21/683 ,  H01L23/538 ,  H01L23/498

    Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

    EVOLVED NODE-B, USER EQUIPMENT, AND METHODS FOR PAGING USING A BITMAP OF PAGING INDICATORS
    3.
    发明申请
    EVOLVED NODE-B, USER EQUIPMENT, AND METHODS FOR PAGING USING A BITMAP OF PAGING INDICATORS 有权
    演示节点B，用户设备和使用寻呼指示符的寻呼方法

    公开(公告)号：US20170064671A1

    公开(公告)日：2017-03-02

    申请号：US14834963

    申请日：2015-08-25

    Applicant: Intel Corporation

    Inventor： Mohammad Mamunur Rashid ,  Satish Chandra Jha ,  Tao Wu ,  Rath Vannithamby

    IPC: H04W68/02 ,  H04W4/00 ,  H04W68/00

    CPC classification number: H04W68/02 ,  H04W4/70 ,  H04W68/005

    Abstract: Embodiments of an Evolved Node-B (eNB), User Equipment (UE), and methods for paging are disclosed herein. The eNB may transmit a paging message that may include paging identifiers to indicate an intention of the eNB to send downlink data to the first group of UEs. The paging message may further include a bitmap of paging indicators to indicate whether the eNB intends to send downlink data to a second group of UEs. The paging message may include the bitmap when a length of the bitmap is less than a combined length of paging identifiers for a paging portion of second group of UEs to which the eNB intends to send downlink data.

    Abstract translation: 本文公开了演进节点B（eNB），用户设备（UE）以及寻呼方法的实施例。 eNB可以发送可以包括寻呼标识符的寻呼消息，以指示eNB向第一组UE发送下行链路数据的意图。 寻呼消息还可以包括寻呼指示符的位图，以指示eNB是否希望向第二组UE发送下行链路数据。 当位图的长度小于eNB旨在发送下行链路数据的第二组UE的寻呼部分的寻呼标识符的组合长度时，寻呼消息可以包括位图。

    Reduced capacitance land pad
    5.
    发明授权
    Reduced capacitance land pad 有权

    公开(公告)号：US10433421B2

    公开(公告)日：2019-10-01

    申请号：US13727439

    申请日：2012-12-26

    Applicant: INTEL CORPORATION

    Inventor： Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

    IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34

    Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

    Chip package incorporating interfacial adhesion through conductor sputtering
    8.
    发明授权
    Chip package incorporating interfacial adhesion through conductor sputtering 有权
    通过导体溅射结合界面粘合的芯片封装

    公开(公告)号：US09331017B2

    公开(公告)日：2016-05-03

    申请号：US14506357

    申请日：2014-10-03

    Applicant: Intel Corporation

    Inventor： Tao Wu ,  Islam A. Salama

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/525 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

    Abstract translation: 本公开一般涉及可以包括制造芯片封装的方法的电子设备和方法。 1.一种绝缘体层，包括绝缘体材料，所述绝缘体层相对于第一导电线定位，相对于所述绝缘体层形成第二导电线，其中所述绝缘体层位于所述第一导电线和所述第二导电线之间，形成 所述绝缘体层在所述第一导电线和所述第二导电线之间的开口，所述开口内的所述绝缘体材料中的至少一些被暴露，以及将导体化学键合到所述开口内的所述至少一些所述绝缘体材料，其中， 导体将第一导线电耦合到第二导线。

    Reduced capacitance land pad
    10.
    发明授权
    Reduced capacitance land pad 有权

    公开(公告)号：US11516915B2

    公开(公告)日：2022-11-29

    申请号：US16559286

    申请日：2019-09-03

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

    IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/34 ,  H05K1/02

    Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

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