公开(公告)号：US11552019B2

公开(公告)日：2023-01-10

申请号：US16299415

申请日：2019-03-12

申请人： Intel Corporation

发明人： Haifa Hariri ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Islam A. Salama

IPC分类号： H01L23/538 ,  H01L23/31

摘要： Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

公开(公告)号：US11508662B2

公开(公告)日：2022-11-22

申请号：US16322423

申请日：2016-09-30

申请人： Intel Corporation

发明人： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

摘要： A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US10707168B2

公开(公告)日：2020-07-07

申请号：US16182277

申请日：2018-11-06

申请人： Intel Corporation

发明人： Amruthavalli Pallavi Alur ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Islam A. Salama ,  Robert L. Sankman

IPC分类号： H01L23/492 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H01L23/31 ,  H01L21/66 ,  H01L21/683 ,  H01L25/11

摘要： An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

公开(公告)号：US09505607B2

公开(公告)日：2016-11-29

申请号：US14671549

申请日：2015-03-27

申请人： Intel Corporation

发明人： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

IPC分类号： B81B3/00 ,  B81C1/00

CPC分类号： B81B7/0077 ,  B81C2203/0109

摘要： Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

摘要翻译： 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

公开(公告)号：US09331017B2

公开(公告)日：2016-05-03

申请号：US14506357

申请日：2014-10-03

申请人： Intel Corporation

发明人： Tao Wu ,  Islam A. Salama

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/525 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

摘要翻译： 本公开一般涉及可以包括制造芯片封装的方法的电子设备和方法。 1.一种绝缘体层，包括绝缘体材料，所述绝缘体层相对于第一导电线定位，相对于所述绝缘体层形成第二导电线，其中所述绝缘体层位于所述第一导电线和所述第二导电线之间，形成 所述绝缘体层在所述第一导电线和所述第二导电线之间的开口，所述开口内的所述绝缘体材料中的至少一些被暴露，以及将导体化学键合到所述开口内的所述至少一些所述绝缘体材料，其中， 导体将第一导线电耦合到第二导线。

公开(公告)号：US12046560B2

公开(公告)日：2024-07-23

申请号：US17555222

申请日：2021-12-17

申请人： Intel Corporation

发明人： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US09952823B2

公开(公告)日：2018-04-24

申请号：US15171833

申请日：2016-06-02

申请人： Intel Corporation

发明人： Johanna M. Swan ,  Uygar Avci ,  Islam A. Salama ,  Ravi Pillarisetty

IPC分类号： G06F3/14 ,  G09F9/302 ,  G09F9/35 ,  H01L27/32 ,  G09G3/20 ,  G02F1/1333 ,  G02F1/1345 ,  G09G5/00 ,  G09G5/14

CPC分类号： G06F3/1446 ,  G02F1/13336 ,  G02F1/1345 ,  G09F9/3026 ,  G09F9/35 ,  G09G3/20 ,  G09G5/003 ,  G09G5/14 ,  G09G2300/026 ,  G09G2320/02 ,  G09G2340/14 ,  G09G2360/04 ,  H01L27/3293

摘要： Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.

公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC分类号： H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC分类号： H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

摘要： A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20170036301A1

公开(公告)日：2017-02-09

申请号：US14909724

申请日：2015-03-06

申请人： INTEL CORPORATION

发明人： Chong Zhang ,  Islam A. Salama

IPC分类号： B23K26/082 ,  B23K26/382 ,  H01S3/00

CPC分类号： B23K26/082 ,  B23K26/0821 ,  B23K26/382 ,  B23K2101/42 ,  G02B26/101 ,  G02B26/124 ,  H01S3/0071 ,  H01S3/1611 ,  H01S3/1643 ,  H01S3/2232

摘要： Embodiments of the present disclosure are directed towards an acousto-optics deflector and mirror for laser beam steering and associated techniques and configurations. In one embodiment, a laser system may include an acousto-optics module to deflect a laser beam in a first scanning direction of the laser beam on an integrated circuit (IC) substrate when the IC substrate is in a path of the laser beam and a mirror having at least one surface to receive the laser beam from the acousto -optics module, the mirror to move to control position of the laser beam in a second scanning direction, wherein the second scanning direction is substantially perpendicular to the first scanning direction. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例针对用于激光束转向的声光偏转器和反射镜以及相关技术和配置。 在一个实施例中，激光系统可以包括声光模块，以在IC基板处于激光束的路径中时将激光束的第一扫描方向上的激光束偏转到集成电路（IC）基板上，并且 反射镜具有至少一个表面以接收来自声光模块的激光束，反射镜在第二扫描方向上移动到激光束的控制位置，其中第二扫描方向基本上垂直于第一扫描方向。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC分类号： H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

摘要： A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.