Invention Grant
US09576683B2 Systems and methods for hard error reduction in a solid state memory device
有权
在固态存储器件中硬损失减少的系统和方法
- Patent Title: Systems and methods for hard error reduction in a solid state memory device
- Patent Title (中): 在固态存储器件中硬损失减少的系统和方法
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Application No.: US14178201Application Date: 2014-02-11
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Publication No.: US09576683B2Publication Date: 2017-02-21
- Inventor: Yunxiang Wu , Yu Cai , Erich F. Haratsch
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Cesari & Reed, LLP
- Agent Kirk A. Cesari
- Main IPC: G11C29/52
- IPC: G11C29/52 ; G11C11/56 ; G11C16/26 ; G11C16/34 ; G11C16/10 ; G11C16/04 ; G11C13/00 ; G06F11/10 ; G06F3/06 ; G11C29/02 ; G11C29/42 ; G11C7/14 ; G11C29/04
Abstract:
Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Public/Granted literature
- US20150220388A1 Systems and Methods for Hard Error Reduction in a Solid State Memory Device Public/Granted day:2015-08-06
Information query
