公开(公告)号：EP1435111B1

公开(公告)日：2010-12-08

申请号：EP02785528.7

申请日：2002-10-08

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  S.O.I.Tec Silicon on Insulator Technologies

发明人： ASPAR, Bernard ,  LAGAHE, Chrystelle ,  GHYSELEN, Bruno

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L2221/68322

摘要： The invention concerns a method for making (1) thin layers (5) containing microcomponents (6) using a substrate. Said method comprises in particular, for each layer (5), the following steps: a) local implantation of at least a gaseous species in said substrate (1) perpendicular to a plurality of implantation zones defined on the surface of the substrate (1), avoiding, by adequate selection of the depth and the shape of said implantation zones, degradation of said surface of the substrate (1) during the step b); b) producing microcomponents (6) in the surface layer (5) of the substrate (1) delimited by the implanting depth; and c) separating the substrate (1) in two parts, one part containing the surface layer (5) including said microcomponents (6), and the other the rest of the substrate (1). The invention is useful for producing microcomponents to be integrated on supports different from those used for their manufacture.

公开(公告)号：EP4303175A1

公开(公告)日：2024-01-10

申请号：EP23183245.2

申请日：2023-07-04

申请人： SOITEC ,  Commissariat à l'énergie atomique et aux énergies alternatives

发明人： GHYSELEN, Bruno ,  SALVETAT, Thierry ,  BERRE, Guillaume ,  RIEUTORD, François

IPC分类号： B81C1/00

摘要： La présente invention concerne un procédé de fabrication d'une structure comprenant une pluralité de membranes chacune surplombant une cavité, le procédé de fabrication comprenant les étapes suivantes :
a) une étape de formation d'une pluralité de cavités débouchant au niveau d'une face avant d'un substrat support, les cavités présentant une profondeur et une aire dans le plan de la face avant, et étant espacées d'un espacement ;
b) une étape d'assemblage par collage direct d'un substrat donneur sur le substrat support, au niveau de leurs faces avant respectives, de manière à sceller les cavités sous vide, le collage direct étant hydrophile et impliquant un nombre donné de monocouches d'eau à une interface de contact entre les substrats ;
c) une étape de transfert d'une couche mince issue du substrat donneur sur le substrat support, ladite couche mince composant les membranes à l'aplomb des cavités.
Une aire spécifique est définie autour de chaque cavité, dans le plan de l'interface de contact, et s'exprime en fonction de la moitié de l'espacement. Le procédé de fabrication est remarquable en ce que l'aire, la profondeur de chaque cavité, et l'aire spécifique sont définies à l'étape a) pour satisfaire la relation suivante : S / A = (P atm × p) / (N × 10 15 × k B × T), avec P atm la pression atmosphérique, N le nombre de monocouches d'eau à l'interface de contact, k B la constante de Boltzmann et T la température ambiante.

公开(公告)号：EP1285461B1

公开(公告)日：2017-01-25

申请号：EP01940623.0

申请日：2001-05-29

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： ASPAR, Bernard ,  LAGAHE, Chrystelle ,  RAYSSAC, Olivier ,  GHYSELEN, Bruno

IPC分类号： H01L21/762 ,  H01L21/20 ,  H01L21/78 ,  H01L21/34

CPC分类号： H01L21/76254 ,  H01L2221/68368

公开(公告)号：EP1378004B1

公开(公告)日：2019-01-16

申请号：EP02732807.9

申请日：2002-04-11

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： ASPAR, Bernard ,  MORICEAU, Hubert ,  RAYSSAC, Olivier ,  GHYSELEN, Bruno

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/306 ,  H01L21/265 ,  H01L21/304 ,  H01L21/68 ,  H01L21/78 ,  B23B31/00

公开(公告)号：EP1631984B1

公开(公告)日：2017-08-23

申请号：EP04767238.1

申请日：2004-06-03

申请人： Soitec ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： AULNETTE, Cécile ,  BATAILLOU, Benoît ,  GHYSELEN, Bruno ,  MORICEAU, Hubert

IPC分类号： H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76254 ,  H01L21/76259

公开(公告)号：EP1523773B1

公开(公告)日：2010-09-22

申请号：EP03763889.7

申请日：2003-07-16

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/76259

公开(公告)号：EP1668693A1

公开(公告)日：2006-06-14

申请号：EP04769613.3

申请日：2004-09-30

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： DAVAL, Nicolas ,  GHYSELEN, Bruno ,  AULNETTE, Cécile ,  RAYSSAC, Olivier ,  CAYREFOURCQ, Ian

IPC分类号： H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/2007 ,  H01L21/76254 ,  Y10S438/933

摘要： The invention provides a method of producing a structure comprising a thin layer (2') of semiconductive material on a support substrate (20), said thin layer (2') being obtained from a donor substrate (10) comprising an upper layer (2) of semiconductor material, the method being characterized in that it comprises: - forming on said upper layer (2) a bonding layer (3) of a material that accepts diffusion of an element of the material of the upper layer (2); - cleaning said bonding layer (3) for mastering its bonding adhesion; - bonding the donor substrate (10), from the side of the bonding layer (3) previously formed on the upper layer (2) and cleaned, to the support substrate (20); and - diffusing said element from the upper layer into the bonding layer to homogenize the concentration of said element in the bonding layer and said upper layer, to constitute said thin layer (2') of the structure with said bonding layer and said upper layer.

公开(公告)号：EP1644969A1

公开(公告)日：2006-04-12

申请号：EP04767657.2

申请日：2004-07-12

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  AKATSU, Takeshi ,  FONTANIERE, Richard

IPC分类号： H01L21/265 ,  H01L21/762

CPC分类号： H01L21/26506 ,  H01L21/76254

摘要： The invention relates to a method for implantation in a wafer comprising at least one layer having an irregular surface, whereby the implantation is performed through said irregular surface. The invention is characterised in that a coating step is performed prior to the implantation step, consisting in coating the irregular surface with a coating layer in order to increase the uniformity of the implantation depth.

公开(公告)号：EP1547143A2

公开(公告)日：2005-06-29

申请号：EP03784416.4

申请日：2003-08-11

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  AULNETTE, Cécile ,  OSTERNAUD, Bénédite

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L21/02238 ,  H01L21/02255 ,  H01L22/20

摘要： The invention relates to a method of preparing a thin layer of semiconductor material, the method including a step (1050') of correcting the thickness of the layer, said step of correcting thickness of the layer itself comprising the following operations: acquiring a measured thickness profile of the layer; deducing thickness correction specifications from the measured thickness profile; and correcting the thickness of the layer in accordance with said specifications; the method being characterized in that thickness correction implements a technique which simultaneously treats the entire surface of the layer, while locally and selectively adapt layer thickness in different regions of the layer surface. The invention also relates to an associated machine.

公开(公告)号：EP1522097A2

公开(公告)日：2005-04-13

申请号：EP03762850.0

申请日：2003-07-09

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  AULNETTE, Cécile ,  OSTERNAUD, Bénédicte

IPC分类号： H01L21/762

CPC分类号： H01L21/76259 ,  H01L21/76254

摘要： Method of producing a structure comprising a thin layer of semiconductor material obtained from a wafer (10), the wafer (10) comprising a lattice parameter matching layer (2) comprising an upper layer of semiconductor material having a first lattice parameter, a film (3) of semiconductor material which has a nominal lattice parameter substantially different from the first lattice parameter and is strained by the matching layer (2), a relaxed layer (4) having a nominal lattice parameter substantially identical to the first lattice parameter, the metod comprising transfer of the relaxed layer (4) and the strained film (3) to a receiving substrate (5). Structures produced according to one of the processes according to the invention.