公开(公告)号：EP3394729A1

公开(公告)日：2018-10-31

申请号：EP16879791.8

申请日：2016-11-23

申请人： Intel Corporation

发明人： ANDERSON, Cristina S. ,  CORNEA-HASEGAN, Marius A. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  ASTAFEV, Nikita ,  CHARNEY, Mark J. ,  GIRKAR, Milind B. ,  GRADSTEIN, Amit ,  RUBANOVICH, Simon ,  SPERBER, Zeev

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F7/4876 ,  G06F7/485 ,  G06F7/49915

摘要： An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.

公开(公告)号：EP3238043A1

公开(公告)日：2017-11-01

申请号：EP15873965.6

申请日：2015-11-23

申请人： Intel Corporation

发明人： HUGHES, Christopher J. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  GIRKAR, Milind B.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30047 ,  G06F9/30112 ,  G06F9/3834 ,  G06F9/3838

摘要： An apparatus and method are described for performing conflict detection operations. For example, one embodiment of a processor comprises: a first source vector register to store a first set of data elements; a second source vector register to store a second set of data elements; conflict detection logic to perform a specified comparison operation comparing each of the first set of data elements with specified data elements from the second set and generating a set of comparison results, the comparison operation to be selected from a group consisting of a greater than comparison, a less than comparison, a greater than or equal to comparison, a less than or equal to comparison, and a not equal to comparison.

摘要翻译： 描述了用于执行冲突检测操作的设备和方法。 例如，处理器的一个实施例包括：第一源向量寄存器，用于存储第一组数据元素; 第二源向量寄存器，用于存储第二组数据元素; 冲突检测逻辑，用于执行指定的比较操作，将第一组数据元素中的每一个与来自第二组中的指定数据元素进行比较，并且生成一组比较结果，比较操作从包括大于比较， 小于比较，大于或等于比较，小于或等于比较以及不等于比较。

公开(公告)号：EP3394730A1

公开(公告)日：2018-10-31

申请号：EP16879792.6

申请日：2016-11-23

申请人： Intel Corporation

发明人： ANDERSON, Cristina S. ,  CORNEA-HASEGAN, Marius A. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  ASTAFEV, Nikita ,  CHARNEY, Mark J. ,  GIRKAR, Milind B. ,  GRADSTEIN, Amit ,  RUBANOVICH, Simon ,  SPERBER, Zeev

IPC分类号： G06F9/30

CPC分类号： G06F7/485

摘要： An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.

公开(公告)号：EP3238031A1

公开(公告)日：2017-11-01

申请号：EP15873977.1

申请日：2015-11-23

申请人： Intel Corporation

发明人： OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  TOLL, Bret L. ,  CORBAL SAN ADRIAN, Jesus ,  CHARNEY, Mark J. ,  GIRKAR, Milind B.

IPC分类号： G06F9/30 ,  G06F7/485

CPC分类号： G06F9/30036 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30018

摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

摘要翻译： 在若干实施例中，指令集体系结构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的矢量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的矢量无符号整数加法。 在一个实施例中，对于有符号和无符号指令都支持打包的双字和四字整数。

公开(公告)号：EP3529695A1

公开(公告)日：2019-08-28

申请号：EP16919077.4

申请日：2016-10-20

申请人： INTEL Corporation

发明人： VALENTINE, Robert ,  RYVCHIN, Galina ,  MAJCHER, Piotr ,  CHARNEY, Mark J. ,  OULD-AHMED-VALL, Elmoustapha ,  CORBAL, Jesus ,  GIRKAR, Milind B. ,  SPERBER, Zeev ,  RUBANOVICH, Simon ,  GRADSTEIN, Amit

IPC分类号： G06F9/30

公开(公告)号：EP3394726A1

公开(公告)日：2018-10-31

申请号：EP16879713.2

申请日：2016-11-21

申请人： Intel Corporation

发明人： JHA, Ashish ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  GIRKAR, Milind B.

IPC分类号： G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3455

摘要： A processor comprises a plurality of vector registers, and an execution unit, operatively coupled to the plurality of vector registers, the execution unit comprising a logic circuit implementing a load instruction for loading, into two or more vector registers, two or more data items associated with a data structure stored in a memory, wherein each one of the two or more vector registers is to store a data item associated with a certain position number within the data structure.

公开(公告)号：EP3238047A1

公开(公告)日：2017-11-01

申请号：EP15873992.0

申请日：2015-11-24

申请人： Intel Corporation

发明人： OULD-AHMED-VALL, Elmoustapha ,  HUGHES, Christopher J. ,  VALENTINE, Robert ,  GIRKAR, Milind B.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/467

摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode, and execution hardware to execute the decoded instruction to reset data speculative execution (DSX) tracking hardware to track speculative memory accesses, clear a DSX status indication in a DSX status register, and commit all speculatively executed stores of the DSX region and thereby end a DSX region.

摘要翻译： 描述了用于数据推测执行（DSX）的系统，方法和装置。 在一些实施例中，用于执行DSX的硬件装置包括对指令进行解码的硬件解码器，包括操作码的指令以及执行解码的指令以重置数据推测执行（DSX）跟踪硬件以跟踪推测性存储器访问的执行硬件， 清除DSX状态寄存器中的DSX状态指示，并提交所有推测性执行的DSX区域存储，从而结束DSX区域。

公开(公告)号：EP3238032A1

公开(公告)日：2017-11-01

申请号：EP15873991.2

申请日：2015-11-24

申请人： Intel Corporation

发明人： OULD-AHMED-VALL, Elmoustapha ,  HUGHES, Christopher J. ,  VALENTINE, Robert ,  GIRKAR, Milind B. ,  IDO, Hideki ,  WU, Youfeng ,  WANG, Cheng

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/528 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863

摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

摘要翻译： 描述了用于数据推测执行（DSX）的系统，方法和装置。 在一些实施例中，用于执行DSX的硬件设备包括：硬件解码器，用于解码指令，包括操作码和操作数以存储回退地址的一部分的指令;执行硬件以执行解码的指令以启动数据推测执行 （DSX）区域，通过激活DSX跟踪硬件来跟踪推测性内存访问并检测DSX区域中的排序违规，并存储回退地址。

公开(公告)号：EP3394735A1

公开(公告)日：2018-10-31

申请号：EP16879684.5

申请日：2016-11-18

申请人： Intel Corporation

发明人： JHA, Ashish ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  GIRKAR, Milind B.

IPC分类号： G06F9/38 ,  G06F15/80

CPC分类号： G06F15/8007 ,  G06F9/30 ,  G06F9/30098 ,  G06F9/3016

摘要： An Aggregate Scatter instruction is described. A processor may include a memory interface and a register to store data elements of a data structure. The data elements may be contiguously stored in a first location in a memory accessible via the memory interface. The processor may further include a decoder to decode an aggregate scatter instruction specifying a store operation for the data structure and an execution unit to contiguously store the data elements to a second storage location in the memory in response to the decoded aggregate scatter instruction. The second storage location may be identified by a starting memory address of the second storage location.

公开(公告)号：EP3238038A1

公开(公告)日：2017-11-01

申请号：EP15874027.4

申请日：2015-11-25

申请人： Intel Corporation

发明人： CORBAL, Jesus ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  GIRKAR, Milind B. ,  TOLL, Bret L. ,  ESPASA, Roger ,  SOLE, Guillem ,  BALART, Jairo ,  HICKMAN, Brian

IPC分类号： G06F9/30 ,  G06F7/76

CPC分类号： G06F9/30036 ,  G06F7/764 ,  G06F9/30032 ,  G06F15/8053 ,  G06F15/8084 ,  G06F17/30952 ,  G06F2209/462

摘要： An apparatus and method for performing a vector permute. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element and to responsively copy the source data element to the corresponding destination data element in the destination vector register.

摘要翻译： 一种执行向量置换的装置和方法。 例如，处理器的一个实施例包括：源向量寄存器，用于存储多个源数据元素; 目的地矢量寄存器，用于存储多个目的地数据元素; 控制向量寄存器，用于存储多个控制数据元素，每个控制数据元素对应于目的地数据元素之一并且包括指示源数据元素是否要被复制到相应的目的地数据元素的N位值; 矢量置换逻辑，用于将每个控制数据元素的N位值与立即数的N位部分进行比较，以确定是否将源数据元素复制到对应的目的地数据元素，其中如果N位值匹配，则向量置换 逻辑是使用包含在控制数据元素中的索引值来识别源数据元素并且响应地将源数据元素复制到目的地向量寄存器中的相应目的地数据元素。