利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.009 秒)

    VOLTAGE SUPPLY CIRCUIT AND METHOD OF CONTROLLING THE SAME
    1.
    发明公开
    VOLTAGE SUPPLY CIRCUIT AND METHOD OF CONTROLLING THE SAME 审中-公开
    电源电路及其控制方法

    公开(公告)号：EP1164454A4

    公开(公告)日：2003-06-11

    申请号：EP00987676

    申请日：2000-12-21

    申请人： SONY CORP

    发明人： HASHIGUCHI AKIHIKO

    IPC分类号： G05F1/46 ,  G06F1/26 ,  G06F1/32 ,  H02M3/28 ,  G05F1/10

    CPC分类号： G06F1/3296 ,  G05F1/466 ,  G06F1/26 ,  G06F1/3203 ,  H02M3/28 ,  Y02D10/172

    摘要： A voltage supply circuit capable of dealing with an abrupt change of a load by controlling an amount of increase of a power source voltage to be larger than an amount of reduction, supplying a stable operating power source voltage, and realizing lower power consumption while maintaining normal operation of a semiconductor integrated circuit is provided. By providing a replica circuit (20), detecting a delay time of a critical path of an LSI (10), comparing a delay time detected by a control circuit (50) with a predetermined reference value, performing control to raise a voltage (VDD) supplied to the LSI (10) when the delay time is larger than the reference value as a result of the comparison and to lower the voltage (VDD) supplied to the LSI (10) when the delay time is smaller than the reference value, and making the amount of increase at the time of raising the supplied voltage larger than the amount of reduction at the time of lowering it, when the supplied voltage (VDD) becomes smaller than the reference value, it can be quickly restored to be larger than the reference value, the time when operating error of the LSI (10) may occur can be greatly shortened, and the operational stability of the voltage supply circuit can be improved.

    Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen
    3.
    发明公开
    Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen 失效
    电路，用于调整互连半导体电路的信号延迟时间。

    公开(公告)号：EP0057351A2

    公开(公告)日：1982-08-11

    申请号：EP82100160.9

    申请日：1982-01-12

    申请人： International Business Machines Corporation

    发明人： Dorler, Jack Arthur ,  Jenkins, Michael Owen ,  Mosley, Joseph Michael ,  Weitzel, Stephen Douglas

    IPC分类号： G05F1/46

    CPC分类号： G05F1/466

    摘要： Bei dieser Schaltung, die als Regelschaltung auf jedem Halbleiterchip vorgesehen ist und eine Phasenvergleichsschaltung enthält, in der die Frequenz eines den Sollwert der Signalverzögerung charakterisierenden, extern zugeführten Impulszuges mit der Frequenz eines auf dem Halbleiterchips befindlichen steuerbaren Oszillators verglichen wird, ist eine Zusatzschaltung vorgesehen. Sie ist an die Phasenvergleichsschaltung angeschlossen und besitzt drei Ausgänge, um anzuzeigen, ob die Frequenz des steuerbaren Oszillators kleiner, gleich oder größer als die des extern zugeführten lmpulszuges ist. Die Zusatzschaltung ist aus drei Verknüpfungsgliedern aufgebaut. Die Ausgänge der beiden Verknüpfungsglieder, die anzeigen, daß die Frequenz des steuerbaren Oszillators höher bzw. niedriger ist als die des extern zugeführten Impulszuges, sind an das dritte Verknüpfungsglied, das Frequenzgleichheit anzeigt, angeschlossen. Die Verknüpfungsglieder sind als NOR-Glieder realisiert.

    摘要翻译： 在该电路中，其被提供为每一个半导体芯片上的控制电路，以及包括其中的信号延迟特征的目标值的频率，外部提供的脉冲序列与位于半导体芯片可控振荡器，提供一个附加电路的频率相比较的相位比较电路。 它被连接到相位比较电路和具有三个输出，以指示该可控振荡器的频率是否比所述外部提供的lmpulszuges小于，等于或更大。 附加电路由三个逻辑门。 两个栅极，这表明，所述可控振荡器的频率是高于或低于所述外部提供的脉冲序列的较低的输出，被连接到第三栅极，表明连接的频率相等。 栅极被实现为NOR门。

    Digital timing signal generator and voltage regulator circuit
    4.
    发明公开
    Digital timing signal generator and voltage regulator circuit 失效
    Digitalimpulssignalgenerator和Spannungsreglerkreis。

    公开(公告)号：EP0264691A2

    公开(公告)日：1988-04-27

    申请号：EP87114416.8

    申请日：1987-10-02

    申请人： ABBOTT LABORATORIES

    发明人： Davis, Charles Lawrence

    IPC分类号： G05F1/46 ,  H03K19/003

    CPC分类号： G05F1/466

    摘要： A digital timing signal generator and voltage regulator circuit is provided. In one embodiment the circuit includes a delay line. The delay line opera­ting voltage is derived from digitally encoded power/­timing signals transmitted by an isolated logic control circuit. The delay line receives and propagates the digitally encoded signals. Outputs of selected stages of the delay line are tapped to provide multiphasic timing signals for use by associated logic circuits. A plurality of gates having inputs connected to various stages of the delay line receive selected timing signals as they propagate along the delay line. Increases in the operating voltage cause the selected timing signals to sequentially activate the gates. The output of each activated gate then goes high and current flows through an associated load resistor connected between the output of the gate and ground to continuously load the supply voltage and thereby regulate it. In variations of this embodiment, two and three levels of gates and load resistors are provided to progressively load the supply voltage and thereby provide additional regulation thereof. In another embodiment, a ring-oscillator comprised of CMOS inverters generates the timing signals. The ring oscillator consumes current in approximately a square relationship with increases in its supply voltage and thereby regulates the voltage.

    摘要翻译： 提供数字定时信号发生器和电压调节器电路。 在一个实施例中，电路包括延迟线。 延迟线工作电压源自由隔离逻辑控制电路发送的数字编码功率/定时信号。 延迟线接收并传播数字编码信号。 对延迟线的选定级的输出进行抽头以提供多相定时信号供相关逻辑电路使用。 具有连接到延迟线的各个级的输入的多个门在沿着延迟线传播时接收所选择的定时信号。 工作电压的增加会使选定的定时信号依次启动门。 然后，每个激活的栅极的输出变高，并且电流流过连接在栅极输出端和地之间的相关联的负载电阻器，以连续地加载电源电压并从而调节它。 在该实施例的变型中，提供两级和三级栅极和负载电阻器以逐渐加载电源电压，从而提供其额外的调节。 在另一个实施例中，由CMOS反相器组成的环形振荡器产生定时信号。 环形振荡器以其电源电压的增加与大致正方形的关系消耗电流，从而调节电压。

    Delay regulation circuit
    5.
    发明公开
    Delay regulation circuit 失效
    Schaltung zum Angleichen derSignalverzögerungszeiten。

    公开(公告)号：EP0229726A1

    公开(公告)日：1987-07-22

    申请号：EP87300348.7

    申请日：1987-01-16

    申请人： TANDEM COMPUTERS INCORPORATED

    发明人： Chengson, David P. ,  Wang, William H.

    IPC分类号： G05F1/46 ,  H03K19/00 ,  H03K19/086

    CPC分类号： G05F1/466 ,  H03K19/00323 ,  H03K19/086

    摘要： An integrated circuit chip (l2) carries a number of electronic circuits (l4), at least one of which includes, in its output stage, a control device (l6) that responds to a reference signal (VREF) to adjust the output current-handling capability of the elect­ronic circuit (l4), thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference signal (VREF) is generated by a digital-­to-analog circuit (l8) that is also formed on the chip (l2). The digital-to-analog circuit (l8) is coupled to a number of contact elements (l,2,3) disposed on an outer surface of the package (8) containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

    摘要翻译： 用于调节由在半导体芯片上制造的并具有用于提供输出电流的输出级的电子电路表现的信号传播延迟的装置包括耦合到输出级的电路（16），并可操作以限制输出电流 响应于参考信号的范围。 第二电路（18）耦合到第一电路并且被预置为选择性地提供多个参考信号中的一个。 多个参考信号中的每一个限定由输出级提供的可操作的输出电流范围。 参考电压是一个电压。

    Input signal responsive pulse generating and biasing circuit for integrated circuits
    6.
    发明公开
    Input signal responsive pulse generating and biasing circuit for integrated circuits 失效
    集成电路的输入信号响应脉冲发生和偏置电路

    公开(公告)号：EP0084146A3

    公开(公告)日：1984-10-03

    申请号：EP82111812

    申请日：1982-12-20

    申请人： International Business Machines Corporation

    发明人： Lewis, Scott Clarence

    IPC分类号： H03K05/15 ,  G05F01/46

    CPC分类号： H03K5/15 ,  G05F1/466 ,  G05F3/247

    摘要： A signal generating circuit for an integrated circuit device responsive to first (CS) and second (DATA IN) externally applied input signals occurring at a predetermined time interval In which the performance of a first input signal responsive circuit (12) is made to vary inversely with respect to the performance of other internal signal generating circuits (10,18, TC) such that internally generated signals will occur at a predetermined time with respect to the external input signals regardless of the influence of variable parameters. Power dissipation of the first input signal responsive circuit also varies inversely with respect to that of other circuits present on the integrated circuit device so that total power dissipation is minimized.

    Digital timing signal generator and voltage regulator circuit
    9.
    发明公开
    Digital timing signal generator and voltage regulator circuit 失效
    数字时序信号发生器和电压调节器电路

    公开(公告)号：EP0264691A3

    公开(公告)日：1989-05-24

    申请号：EP87114416.8

    申请日：1987-10-02

    申请人： ABBOTT LABORATORIES

    发明人： Davis, Charles Lawrence

    IPC分类号： G05F1/46 ,  H03K19/003

    CPC分类号： G05F1/466

    摘要： A digital timing signal generator and voltage regulator circuit is provided. In one embodiment the circuit includes a delay line. The delay line opera­ting voltage is derived from digitally encoded power/­timing signals transmitted by an isolated logic control circuit. The delay line receives and propagates the digitally encoded signals. Outputs of selected stages of the delay line are tapped to provide multiphasic timing signals for use by associated logic circuits. A plurality of gates having inputs connected to various stages of the delay line receive selected timing signals as they propagate along the delay line. Increases in the operating voltage cause the selected timing signals to sequentially activate the gates. The output of each activated gate then goes high and current flows through an associated load resistor connected between the output of the gate and ground to continuously load the supply voltage and thereby regulate it. In variations of this embodiment, two and three levels of gates and load resistors are provided to progressively load the supply voltage and thereby provide additional regulation thereof. In another embodiment, a ring-oscillator comprised of CMOS inverters generates the timing signals. The ring oscillator consumes current in approximately a square relationship with increases in its supply voltage and thereby regulates the voltage.