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公开(公告)号：EP0427442A2
公开(公告)日：1991-05-15
申请号：EP90311891.7
申请日：1990-10-30
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , Y10S331/03
摘要： Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (Fig. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be dissbled, thereby removing the remaining sections (106) of the oscillator from the closed loop path. The NOR gates are implemented as a differential amplifier (Fig. 5) having two transistors (610 and 612) in the input leg and one transistor (616) with its base connected to a regulated voltage (Vr) in the opposite leg. The output of the NOR gate is taken from the collectors of the input transistors. The propagation delay of the oscillator signal through the gate is minimal because, to switch the output state of the gate, only the state of one of the input transistors (610 or 612) must be changed. The short propagation delay through the gate permits high frequency operation, as well as the ability to program small incremental steps in the center frequency of the oscillator.
摘要翻译： 环形振荡器的每个部分（例如102）由三个双输入NOR门组成; 前馈路径（108）中的一个，反馈路径（112）中的一个，以及交叉路径（110）中的一个。 通过启用和禁用适当的门来控制振荡器的中心频率，使得形成单个闭环路径。 前馈和交叉路径中的门直接从控制电路（图2）启用或禁用（禁止输入保持高电平）。 然而，反馈路径中的门间接启用和禁用。 为了启用特定反馈路径门（例如118），对应的交叉门（116）被禁用，或者相应的前馈门被禁用（114），并且下一部分中的交叉门（122）被使能。 后来导致下一部分中的反馈门（124）被消除，从而从闭环路径中去除振荡器的剩余部分（106）。 NOR门被实现为在输入支路中具有两个晶体管（610和612）的差分放大器（图5）和其基极连接到相对支路中的调节电压（Vr）的一个晶体管（616）。 NOR门的输出取自输入晶体管的集电极。 通过栅极的振荡器信号的传播延迟是最小的，因为为了切换栅极的输出状态，只有输入晶体管（610或612）之一的状态必须改变。 通过栅极的短传播延迟允许高频操作，以及在振荡器的中心频率中编程小增量步长的能力。
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公开(公告)号：EP0294602A3
公开(公告)日：1989-08-09
申请号：EP88107495.9
申请日：1988-05-10
IPC分类号： H03K19/003
CPC分类号： H03K19/00392
摘要： Fault tolerant logic circuitry wherein the logic gate circuits employed therein each include an input circuit portion and a push-pull output circuit portion. The push-pull output circuit portion of each of said logic gates employed in said fault tolerant logic circuitry having the characteristic that when an output of a first logic gate circuit is connected to an output of a second logic gate circuit, said connection between the outputs of said first and second logic gate circuits will provide a predetermined logical function.
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3.发明授权
公开(公告)号：EP0057351B1
公开(公告)日：1984-07-04
申请号：EP82100160.9
申请日：1982-01-12
发明人： Dorler, Jack Arthur , Jenkins, Michael Owen , Mosley, Joseph Michael , Weitzel, Stephen Douglas
IPC分类号： G05F1/46
CPC分类号： G05F1/466
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4.发明公开Driver circuit with means for reducing self-induced switching noise 失效Treiberschaltung mit Mitteln zum Verringern selbstinduzierten Schaltrauschens。
公开(公告)号：EP0097889A2
公开(公告)日：1984-01-11
申请号：EP83105926.6
申请日：1983-06-16
IPC分类号： H03K17/16
CPC分类号： H03K17/16
摘要： For reducing self-induced switching noise a two terminal non-linear impedance means is connected to the collector of an output transistor (T1) of a driver circuit and the reference potential line. It comprises one or more serially connected diodes, which may be formed by the base-collector junctions of bipolar transistors (TS1, TS2).
摘要翻译： 为了减少自感应开关噪声，两端非线性阻抗装置连接到驱动电路的输出晶体管（T1）的集电极和参考电位线。 它包括一个或多个串联二极管，其可以由双极晶体管（TS1，TS2）的基极 - 集电极结形成。
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公开(公告)号：EP0055341A2
公开(公告)日：1982-07-07
申请号：EP81108134.8
申请日：1981-10-09
IPC分类号： H03K19/086
CPC分类号： H03K19/086 , H03K19/0136
摘要： A current controlled gate performing a NOR function utilizes a pair of transistors (T4, T5) acting as current mirrors that receive a DC bias through a large resistor (R B ). This bias occurs when an input transistor (T1, T2) is positive to insure that one of the current mirror transistors (T4, T5) will saturate when the input transistors (T1, T2) are "off" and the other will be driven into saturation when either of the input transistors (T1, T2) is "on". When all inputs are negative, one of the current mirror transistors (T4, T5) saturates thereby reducing the current to the input transistors (T1, T2) effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor (T4, T5). An active push-pull output is produced with a single collector path from input to output.
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公开(公告)号：EP0427442B1
公开(公告)日：1995-09-27
申请号：EP90311891.7
申请日：1990-10-30
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , Y10S331/03
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公开(公告)号：EP0658851A2
公开(公告)日：1995-06-21
申请号：EP94308598.5
申请日：1994-11-22
发明人： Budman, Mark , Jenness, Robert Vincent , Massman, Lloyd Herman , Mosley, Joseph Michael , Wutka, Anthony Dale
IPC分类号： G06F13/40
CPC分类号： G06F13/4063
摘要： A flexible cable assembly for coupling an electronic apparatus, having a port for receiving personal computer cards in accordance with the PCMCIA standard, to at least one peripheral device, said flex cable assembly comprises a personal computer card connector, in accordance with the PCMCIA standard, for connecting into a corresponding port in the electronic apparatus, and a flexible cable connected to the personal computer card connector. The personal computer card connector also comprises an interface to said at least one peripheral device. In accordance with a further aspect of the invention, the flex cable assembly can also couple a first electronic apparatus, to a second electronic apparatus, each having a port for receiving personal computer cards in accordance with the PCMCIA standard. This flex cable assembly comprises (1) a first PCMCIA card connector for connecting into a corresponding port in either the first or second electronic apparatus; (2) a second PCMCIA card connector for connecting into a corresponding port in either the first or second electronic apparatus; and (3) a flex cable coupled between the first and second personal computer card connectors.
摘要翻译： 一种用于将具有用于接收根据PCMCIA标准的个人计算机卡的端口耦合到至少一个外围设备的电子设备的柔性电缆组件，所述柔性电缆组件包括根据PCMCIA标准的个人计算机卡连接器， 用于连接到电子设备中的对应端口，以及连接到个人计算机卡连接器的柔性电缆。 个人计算机卡连接器还包括到所述至少一个外围设备的接口。 根据本发明的另一方面，柔性电缆组件还可以将第一电子设备耦合到第二电子设备，每个电子设备具有根据PCMCIA标准的用于接收个人计算机卡的端口。 该柔性电缆组件包括：（1）用于连接到第一或第二电子设备中相应端口的第一PCMCIA卡连接器; （2）第二PCMCIA卡连接器，用于连接到第一或第二电子设备中的相应端口; 和（3）耦合在第一和第二个人计算机卡连接器之间的柔性电缆。
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8.发明公开All-node switch - an unclocked, unbuffered, asynchronous, switching apparatus 失效Schalterfüralle Knoten，ungepufferte asynchrone Schaltvorrichtung ohne Taktgeber。
公开(公告)号：EP0505695A2
公开(公告)日：1992-09-30
申请号：EP92101705.9
申请日：1992-02-03
发明人： Franaszek, Peter Anthony , Georgiou, Christos John , Lusch, Robert Francis , Mosley, Joseph Michael , Olnowich, Howard Thomas
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L49/101 , H04L49/15 , H04L49/1523 , H04L49/201 , H04L49/25 , H04L49/254 , H04L49/40 , H04L49/555 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is an apparatus for switching input port connections to output port connections quickly and dynamically using a new asynchronous approach to resolve contention. The disclosed ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is completely completely void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays - on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.
摘要翻译： 公开了一种用于使用新的异步方法快速和动态地将输入端口连接切换到输出端口连接以解决争用的装置。 所公开的ALL-NODE（异步，低延迟节点）交换机以两个周期的时间自动路由，以与数据通过交换机传输的高速串行速率相同。 交换机的正常模式在与交换机接口的任何输入和输出端口之间绝对不需要同步。 该交换机完全没有集中控制的时钟和任何数据缓冲。 数据通过开关只遇到三个门延迟 - 片上接收器，多路复用器和片外驱动器。 在芯片上检测和解决争用，但逻辑实现非常简单，门数很少，因此开关设计从不限制门限。 该协议需要几条并行数据线加上两条或三条控制线。
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9.发明公开Integrated high gain voltage controlled oscillator 失效Instgrierter spannungsgesteuerter Oszillator mit hohemVerstärkungsgrad。
公开(公告)号：EP0265666A2
公开(公告)日：1988-05-04
申请号：EP87113820.2
申请日：1987-09-22
CPC分类号： H03K3/0315 , H03L7/0995
摘要： A voltage controlled oscillator is formed of a plurality of cascaded inverter stages in a ring configuration. Each inverter stage is a grounded emitter circuit having an active pull-stage in order to achieve a short stage delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a phase locked loop or other frequency generation system.
摘要翻译： 压控振荡器由环形结构中的多个级联的反相器级形成。 每个逆变器级是具有有源拉动级的接地发射极电路，以便实现短阶段延迟。 环形振荡器的频率由反相器级数确定，增益可通过将外部控制电压耦合到某些逆变器来选择。 VCO可以与单个集成电路一起制造，以及形成锁相环或其他频率发生系统所必需的其它电路。
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公开(公告)号：EP0220577A2
公开(公告)日：1987-05-06
申请号：EP86114061.4
申请日：1986-10-10
IPC分类号： G11C29/00
CPC分类号： G11C29/50012 , G11C7/00 , G11C8/18 , G11C29/50
摘要： A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory (34) is designed to utilize and externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch (18) and starts the memory (34). The addressed memory cells are sensed. When at least one memory cell has data are its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits (36) are stable, a signal (ADV) is sent to the set/reset latch (18) to cause it to be reset. The resetting of the set/reset latch (18) causes an output thereof ot change state. This state change comprises the read complete signal (RC) which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.
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