公开(公告)号：EP3327776A3

公开(公告)日：2018-08-22

申请号：EP17202701.3

申请日：2017-11-21

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L27/11 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/1104 ,  G11C11/4023 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1052 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.

公开(公告)号：EP3216051A4

公开(公告)日：2018-06-06

申请号：EP15849239

申请日：2015-10-09

申请人： SCHOTTKY LSI INC

发明人： CHANG AUGUSTINE WEI-CHUN ,  DERMY PIERRE

IPC分类号： H01L21/8238

CPC分类号： H01L27/0727 ,  H01L27/0255 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/11253 ,  H01L29/66515 ,  H01L29/7833

摘要： This application disclosed a low voltage threshold integrated circuit including a substrate, one or more Schottky barrier diodes (SBDs) formed on the substrate, and two or more complementary transistors formed on the substrate. At least one of the SBDs is integrated within a substantially shallow diffusion bed associated with a drain of at least one of the complementary transistors, and shares a common terminal with the at least one of the complementary transistors. In some implementations, the integrated circuit includes a static random access memory (SRAM) array further including a plurality of bit cells. At least one of the bit cells includes two SBDs, and a latch formed from two cross-coupled inverters each including two CMOS transistors. One of the two SBDs is integrated in a substantially shallow diffusion bed associated with a drain of one of the CMOS transistors of the cross-coupled inverters.

公开(公告)号：EP3311416A1

公开(公告)日：2018-04-25

申请号：EP15895802.5

申请日：2015-06-17

申请人： Intel Corporation

发明人： MEHANDRU, Rishabh ,  MORROW, Patrick ,  KUMAR, Ranjith ,  WEBER, Cory, E. ,  KIM, Seiyon ,  CEA, Stephen, M. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

摘要： Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：EP3293763A1

公开(公告)日：2018-03-14

申请号：EP17186560.3

申请日：2017-08-17

申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

发明人： QIAN, Gang ,  MIAO, Yiming ,  SUN, Yanlin ,  CHEN, Xubo

IPC分类号： H01L27/11 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  G11C11/417 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1112 ,  H01L29/0649

摘要： A semiconductor device includes a semiconductor substrate, a trench isolator portion in the semiconductor substrate, a dummy gate on the semiconductor substrate, a first doped region between the trench isolator portion and the dummy gate in the semiconductor substrate, and a first connecting member electrically connected the dummy gate with the first doped region. With the dummy gate electrically connected to the first doped region, a transistor including the dummy gate is turned off, thereby preventing the occurrence of current leakage and improving the reliability of a memory device having the semiconductor device.

摘要翻译： 一种半导体器件，包括：半导体衬底;半导体衬底中的沟槽隔离器部分;半导体衬底上的伪栅极;半导体衬底中的沟槽隔离器部分和伪栅极之间的第一掺杂区域;以及第一连接构件， 具有第一掺杂区的伪栅极。 通过伪栅极电连接到第一掺杂区域，包括伪栅极的晶体管截止，由此防止电流泄漏的发生并且提高具有该半导体器件的存储器件的可靠性。

公开(公告)号：EP3158576A4

公开(公告)日：2018-02-14

申请号：EP15811255

申请日：2015-06-23

申请人： SYNOPSYS INC

发明人： MOROZ VICTOR ,  KAWA JAMIL

IPC分类号： H01L21/00 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC分类号： G06F17/5072 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

摘要： An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.

公开(公告)号：EP3252817A1

公开(公告)日：2017-12-06

申请号：EP17173723.2

申请日：2017-05-31

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/4966

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

摘要翻译： 一种用于制造半导体器件的方法包括：提供衬底结构，该衬底结构包括衬底，层间介电层，层间介电层中的多个沟槽，该多个沟槽包括用于形成第一晶体管，第二晶体管和第三晶体管的各自栅极结构的第一沟槽，第二沟槽，第三沟槽， 沟槽底部的界面层; 在沟槽的界面层和侧壁上形成高k介电层; 在第三沟槽的高k介电层上形成第一PMOS功函数调整层; 在形成第一PMOS功函数调整层之后，在沟槽中形成第二PMOS功函数调整层; 在形成第二PMOS功函数调整层之后，在沟槽中形成NMOS功函数层; 以及在阻挡层上形成NMOS功函数层和金属栅极层之后，在沟槽中形成阻挡层。

公开(公告)号：EP3246943A1

公开(公告)日：2017-11-22

申请号：EP17171958.6

申请日：2017-05-19

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： WACQUEZ, Romain ,  FOURNIER, Jacques ,  REITA, Carlo

IPC分类号： H01L23/544

CPC分类号： H03K19/00315 ,  G06F21/44 ,  H01L23/544 ,  H01L23/576 ,  H01L27/1104 ,  H01L2223/54413 ,  H01L2223/5444 ,  H01L2223/54473

摘要： Dispositif électronique (100) comportant au moins :
- une pluralité de transistors (102) MOSFET de type FD-SOI, parmi lesquels des premiers transistors (104) sont tels que chaque premier transistor comporte un canal dans lequel une concentration de dopants du même type que ceux présents dans les source et drain dudit premier transistor est supérieure à celle dans le canal de chacun des autres transistors de ladite pluralité de transistors ; et
- un circuit d'identification (106) apte à déterminer un identifiant unique du dispositif électronique à partir d'au moins une caractéristique électrique intrinsèque de chacun des premiers transistors dont la valeur dépend au moins en partie de la conductance dudit premier transistor ;
et dans lequel une grille de chacun des premiers transistors a une longueur inférieure ou égale à environ 20 nm.

摘要翻译： 1。一种电子设备（100），至少包括：多个FD-SOI型MOSFET晶体管（102），其中第一晶体管（104）使得每个第一晶体管包括沟道，其中相同类型的掺杂剂浓度 存在于所述第一晶体管的源极和漏极中的那些大于所述多个晶体管中的每个其他晶体管的沟道中的那些; 以及识别电路（106），其能够根据其值至少部分取决于所述第一晶体管的电导的每个第一晶体管的至少一个固有电特性来确定所述电子设备的唯一标识符; 并且其中每个第一晶体管的栅极具有小于或等于约20nm的长度。

公开(公告)号：EP3032540A4

公开(公告)日：2017-03-15

申请号：EP13891121

申请日：2013-08-06

申请人： RENESAS ELECTRONICS CORP

发明人： NII KOJI

IPC分类号： H01L27/11 ,  G11C8/16 ,  G11C11/412 ,  H01L27/02

CPC分类号： H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

摘要翻译： 在处理图像信息等的芯片中，多端口SRAM与诸如数字信号处理电路的逻辑电路混合在一起。 在这种情况下，例如，在使用3端口的情况下，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 然而，在这种配置中，显然存在一个问题，即当嵌入式SRAM的占用面积减小时，写入和读出端口的数量仅限于一个，并且与差分读出一样快的读出特性不能 预计在单端读出。 本申请的概述是三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如，N阱区域被布置在单元的中心，并且P阱区域 布置在其两侧。

公开(公告)号：EP2104950B1

公开(公告)日：2016-11-16

申请号：EP07858218.6

申请日：2007-12-28

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： VINET, Maud ,  THOMAS, Olivier ,  ROZEAU, Olivier ,  POIROUX, Thierry

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

公开(公告)号：EP3050061A1

公开(公告)日：2016-08-03

申请号：EP14790817.2

申请日：2014-09-24

申请人： Qualcomm Incorporated

发明人： GULATI, Chirag ,  SINHA, Rakesh Kumar ,  CHABA, Ritu ,  YOON, Sei Seung

IPC分类号： G11C11/419 ,  G11C8/08 ,  G11C8/14

CPC分类号： G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

摘要： An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.