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    FELDEFFEKTTRANSISTOR-ANORDNUNG
    6.
    发明公开
    FELDEFFEKTTRANSISTOR-ANORDNUNG 审中-公开
    场效应晶体管布置

    公开(公告)号：EP3014658A1

    公开(公告)日：2016-05-04

    申请号：EP14739705.3

    申请日：2014-06-25

    申请人： Technische Universität Darmstadt

    发明人： SCHWALKE, Udo ,  WESSELY, Frank ,  KRAUSS, Tillmann

    IPC分类号： H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/7838 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/7839 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654

    摘要： The invention relates to a field effect transistor arrangement having a planar channel layer (1) consisting of semiconductor material, the whole surface of the underside of said layer being applied to an upper side of an electrically insulating substrate layer (2) and the upper side of said planar channel layer being covered by an insulation layer (3). The arrangement has a source electrode (6) on a first side edge of the channel layer (1) and a drain electrode (7) on a second side edge of the channel layer (1) and a control electrode (9) arranged above the channel layer (1). An adjusting electrode (5) is arranged on an underside of the substrate layer (2). A contact region (8) between the source and drain electrodes (6) and the planar channel layer (1) is in each case configured as a midgap Schottky barrier. A respective barrier control electrode (10) is arranged in the vicinity of the contact region (8) of the source electrode (6) and of the drain electrode (6). Each barrier control electrode (10) can have a section (11) that projects outwards in the direction of the planar channel layer (1).

    Circuit layout for organic transistors in series or parallel
    9.
    发明公开
    Circuit layout for organic transistors in series or parallel 审中-公开
    Scharungsanordnungfürorganische Transistoren in Reihen- order Parallelbetrieb

    公开(公告)号：EP2731154A2

    公开(公告)日：2014-05-14

    申请号：EP13192088.6

    申请日：2013-11-08

    申请人： Palo Alto Research Center Incorporated

    发明人： NG, Tse Nga ,  Schwartz, David Eric ,  Veres, Janos

    IPC分类号： H01L51/05 ,  H01L27/12

    CPC分类号： H01L51/0554 ,  H01L29/78645

    摘要： Multiple thin film transistors are aligned in serial and parallel orientation. A second source region is disposed between a first source region and a first drain region. A second drain region is disposed between the first source region and the first drain region. The second drain region and the second source region substantially coincide. A first gate is disposed between the first source region and the coinciding second source and second drain regions. A second gate region is disposed between the first drain region and the coinciding second source and second drain regions. An semiconductor is disposed between the first source region, the first drain region, and the coinciding second source and second drain regions. A dielectric material is disposed between the semiconductor substrate and the first and second gates.

    摘要翻译： 多个薄膜晶体管以串联和平行取向对齐。 第二源极区域设置在第一源极区域和第一漏极区域之间。 第二漏极区域设置在第一源极区域和第一漏极区域之间。 第二漏极区域和第二源极区域基本上重合。 第一栅极设置在第一源极区域和重合的第二源极和第二漏极区域之间。 第二栅极区域设置在第一漏极区域和重合的第二源极和第二漏极区域之间。 半导体设置在第一源极区域，第一漏极区域和重合的第二源极和第二漏极区域之间。 介电材料设置在半导体衬底与第一和第二栅极之间。