公开(公告)号：EP2302555B1

公开(公告)日：2016-10-05

申请号：EP10012987.3

申请日：2003-04-14

申请人： Massachusetts Institute of Technology

发明人： Devadas, Srinivas ,  Gassend, Blaise ,  Clarke, Dwaine

IPC分类号： G09C1/00

CPC分类号： G06F21/31 ,  G06F21/72 ,  G06F21/73 ,  G06F21/77 ,  G06F21/79 ,  G06F21/86 ,  G06F2221/2103 ,  G06F2221/2121 ,  G06F2221/2129 ,  G06F2221/2153 ,  G06Q20/3674 ,  G09C1/00 ,  H01L23/544 ,  H01L23/576 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H04L9/0897 ,  H04L9/3278 ,  H04L2209/34 ,  H04L2209/42 ,  H01L2924/00

摘要： A chip and method is provided for operating a chip to generate and use a secret key to decrypt contents of a memory, wherein the method comprises: receiving at a PUF circuit in the chip a challenge stored on the chip; outputting from the PUF circuit a k-bit response; combining in the chip the k-bit response with the content of fuses to produce a key; and receiving the key at a decrypter and decrypting contents of a memory in the chip.

公开(公告)号：EP2113941B1

公开(公告)日：2013-02-13

申请号：EP08155615.1

申请日：2008-05-02

申请人： STMicroelectronics (Research & Development) Limited

发明人： Baxter, Patrick ,  Raynor, Jeffrey

IPC分类号： H01L23/544 ,  H01L27/148 ,  H04N1/32

CPC分类号： H01L27/14625 ,  G01N21/6454 ,  H01L23/544 ,  H01L27/1463 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H04N5/374 ,  H01L2924/00

公开(公告)号：EP2232552A4

公开(公告)日：2012-09-19

申请号：EP07869082

申请日：2007-12-10

申请人： AGERE SYSTEMS INC

发明人： CHECK JOSEPH J ,  HARRIS EDWARD B ,  MANTZ LYLE K II ,  KISER RICHARD R ,  LEITH PATRICIA J

IPC分类号： H01L23/48 ,  H01L23/544

CPC分类号： H01L24/06 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00014

公开(公告)号：EP2387798A2

公开(公告)日：2011-11-23

申请号：EP09774845.3

申请日：2009-12-15

申请人： KHS GmbH

发明人： KEIL, Gernot

IPC分类号： H01L23/544 ,  H01L23/58 ,  H04L9/32

CPC分类号： H01L23/544 ,  H01L23/576 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a method for verifying an identification circuit (5) integrated in a component to be identified, having the following steps: a) entering a primary key in the identification circuit (5), b.) reading a secondary key output by the identification circuit (5) in reaction to the input of the primary key, c.) providing a control key associated with the primary key, d.) comparing the control key to the output secondary key, e.) providing a result of the comparison step, wherein in case of a match of the secondary key to the control key, the component having the identification circuit is identified as an original component, and in the opposite case, as a counterfeit component, and wherein the identification circuit (5) comprises non-conducting, semiconducting, and conducting materials disposed and connected to each other such that at least one electronic circuit configuration is formed, comprising at least one defined mathematical function and configured for determining the secondary key from the primary key inputted into the identification circuit (5), and providing said secondary key for readout, at least using the at least one mathematical function.

公开(公告)号：EP1240668B1

公开(公告)日：2011-08-24

申请号：EP00973889.9

申请日：2000-10-25

申请人： Intel Corporation

发明人： HORIGAN, John, W. ,  MORESCO, Larry, L.

IPC分类号： H01L23/544 ,  H05K1/02

CPC分类号： H05K1/0266 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2924/01004 ,  H05K1/029 ,  H05K3/3436 ,  H05K2201/10734

摘要： An integrated circuit (IC) package includes a substrate, a ground line, and an encoded region. The encoded region provides information based upon selective deposition of solder balls electrically coupled to the ground line.

公开(公告)号：EP1926138A4

公开(公告)日：2011-06-22

申请号：EP05772572

申请日：2005-08-18

申请人： ADVANTEST CORP ,  NAT UNIVERSITY CORP TOHOKU UNVERSITY

发明人： OKAYASU TOSHIYUKI ,  SUGAWA SHIGETOSHI ,  TERAMOTO AKINOBU

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  G01R31/31718 ,  G11C2029/4402 ,  H01L21/76254 ,  H01L22/14 ,  H01L2223/5444 ,  H01L2924/0002 ,  Y10T29/49004 ,  H01L2924/00

公开(公告)号：EP1341214A4

公开(公告)日：2008-10-01

申请号：EP01963464

申请日：2001-09-06

申请人： HITACHI LTD ,  HITACHI ULSI SYS CO LTD

发明人： MURANAKA MASAYA

IPC分类号： G06K19/06 ,  H01L21/66 ,  H01L23/544 ,  H01L21/02 ,  G01R31/28 ,  H01L27/04

CPC分类号： H01L22/00 ,  G05B19/128 ,  G05B2219/31307 ,  G05B2219/45031 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  Y02P90/10 ,  Y02P90/86 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical quantity corresponding to variation in the process of the plurality of identification elements is employed as identification information specific to the semiconductor integrated circuit device.

公开(公告)号：EP0905777B1

公开(公告)日：2008-05-07

申请号：EP98110693.3

申请日：1998-06-10

申请人： Infineon Technologies AG

发明人： Klette, Rüdiger, Dr.

IPC分类号： H01L23/525

CPC分类号： H01L22/22 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  Y10T29/49107 ,  Y10T29/49117 ,  H01L2924/00

公开(公告)号：EP1900026A1

公开(公告)日：2008-03-19

申请号：EP06754629.1

申请日：2006-06-29

申请人： Rohde & Schwarz GmbH & Co. KG

发明人： WANIERKE, Otmar

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for the forgery-proof identification of individual electronic subassemblies. According to said method, the changes in the status of certain storage locations of a memory (2) of an individual electronic subassembly (1) resulting from a specific breakdown of one or several auxiliary functions of said memory (2) are determined, and said changes in status are compared to predetermined memory-characteristic reference changes in the status of specific storage locations of the memory (2) regarding the identity thereof, said reference changes resulting from the specific breakdown of the auxiliary function of the memory (2) of the electronic subassembly (1).

公开(公告)号：EP1807869A2

公开(公告)日：2007-07-18

申请号：EP05800239.5

申请日：2005-09-23

申请人： STMicroelectronics SA

发明人： MARINET, Fabrice

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns the generation of a chip identifier (2) bearing at least one integrated circuit, which consists in providing a cutout of least one conductive path (4) by cutting the chip, the position of the cutting line (3) relative to the chip conditioning the identifier.