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    SEMICONDUCTOR TRANSISTOR WITH PRECISE GEOMETRIES AND RELATED MANUFACTURE METHOD THEREOF
    1.
    发明公开
    SEMICONDUCTOR TRANSISTOR WITH PRECISE GEOMETRIES AND RELATED MANUFACTURE METHOD THEREOF 审中-公开

    公开(公告)号：EP4376095A1

    公开(公告)日：2024-05-29

    申请号：EP23211659.0

    申请日：2023-11-23

    申请人： Invention And Collaboration Laboratory Pte. Ltd.

    发明人： Lu, Chao-Chun

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7853 ,  H01L29/66818

    摘要： A semiconductor transistor includes a semiconductor substrate with an original surface, an active region, a shallow trench isolation region, a shallow trench isolation region, a first conductive region and a second conductive region located within the active region, and a spacer. The active region is formed based on the semiconductor substrate and the active region has a fin structure. The shallow trench isolation region surrounds the active region and a gate structure of the semiconductor transistor crosses over the fin structure. The spacer contacts to a sidewall of the gate structure and on the fin structure. A width of the fin structure under the spacer is wider than that of the fin structure under the gate structure, the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure includes a rounded corner under the spacer.

    TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE
    3.
    发明公开
    TECHNIQUES FOR ACHIEVING MULTIPLE TRANSISTOR FIN DIMENSIONS ON A SINGLE DIE 审中-公开

    公开(公告)号：EP3123517A4

    公开(公告)日：2017-11-29

    申请号：EP14887004

    申请日：2014-03-24

    申请人： INTEL CORP

    发明人： GLASS GLENN A ,  MURTHY ANAND S

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/0924 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785

    摘要： Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

    DUAL WIDTH FINFET
    5.
    发明公开
    DUAL WIDTH FINFET 审中-公开
    FINFET MIT ZWEI VERSCHIEDENEN BREITEN

    公开(公告)号：EP3076433A1

    公开(公告)日：2016-10-05

    申请号：EP15184303.4

    申请日：2015-09-08

    申请人： STMicroelectronics, Inc.

    发明人： LIU, Qing

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

    摘要： A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

    摘要翻译： 公开了一种双宽度SOI FinFET，其中应变翅片的不同部分具有不同的宽度。 制造这种双宽度FinFET的方法需要使用湿化学蚀刻工艺横向凹入源极和漏极区域中的应变翅片，以便在修整源极中的鳍部的宽度的同时保持翅片中的高度应变 和漏极区域小于5nm。 所得到的FinFET在栅极下方的沟道区域中具有鳍的宽部分，以及在源极和漏极区中鳍的较窄部分。 较窄翅片的优点是在外延凸起的源极和漏极区域的生长期间可以更容易地掺杂。

    A method for manufacturing a transistor device and associated device
    6.
    发明公开
    A method for manufacturing a transistor device and associated device 有权
    Verfahren zur Herstellung einer Transistorvorrichtung undzugehörigeVorrichtung

    公开(公告)号：EP2887399A1

    公开(公告)日：2015-06-24

    申请号：EP14151285.5

    申请日：2014-01-15

    申请人： IMEC

    发明人： Rooyackers, Rita ,  Collaert, Nadine ,  Eneman, Geert

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

    CPC分类号： H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

    摘要： A method for manufacturing a transistor device, the method comprising
    a. providing a plurality of parallel nanowires on a substrate;
    b. providing a dummy gate structure over a central portion of the parallel nanowires;
    c. epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion;
    d. providing a filler layer around and on top of the dummy gate structure and the extension portions;
    e. removing the dummy gate structure, in order to create a gate trench, exposing the central portion of the parallel nanowires;
    f. providing spacer structures on the sidewalls of the gate trench, to define a final gate trench;
    g. thinning the parallel nanowires, thereby creating free space in between the nanowires and the spacer structures;
    h. selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and the respective extension portions.

    摘要翻译： 一种制造晶体管器件的方法，该方法包括a。 在衬底上提供多个平行的纳米线; 湾 在平行的纳米线的中心部分上提供虚拟栅极结构; C。 外延生长延伸部分的第二材料，选择性地在平行的纳米线上，在中心部分之外; 天。 在虚拟栅极结构和延伸部分周围和顶部设置填充层; 即 去除伪栅极结构，以便产生栅极沟槽，暴露平行的纳米线的中心部分; F。 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终栅极沟槽; G。 使平行的纳米线变薄，从而在纳米线和间隔结构之间产生自由空间; H。 在平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充自由空间，从而提供量子阱层和相应延伸部分之间的连接。

    Procédé de fabrication d'un transistor MOS à ailette
    7.
    发明公开
    Procédé de fabrication d'un transistor MOS à ailette 审中-公开
    Verfahren zur Herstellung eines Finfet-MOS晶体管

    公开(公告)号：EP2772941A1

    公开(公告)日：2014-09-03

    申请号：EP14157272.7

    申请日：2014-02-28

    申请人： STmicroelectronics SA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    发明人： Morand, Yves ,  Wacquez, Romain ,  Grenouillet, Laurent ,  Le Tiec, Yannick ,  Vinet, Maud

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7856

    摘要： L'invention concerne un procédé de fabrication d'un transistor MOS à ailette à partir d'une structure de type SOI comportant une couche semiconductrice (101) sur une couche d'oxyde de silicium (103) revêtant un support semiconducteur (105), ce procédé comprenant les étapes suivantes : a) former, depuis la surface de la couche semiconductrice (101), au moins une tranchée délimitant au moins une ailette (107) dans la couche semiconductrice (101) et s'étendant jusqu'à la surface du support semiconducteur (105) ; b) graver les flancs d'une partie de la couche d'oxyde de silicium (103) située sous l'ailette (107) de façon à former au moins un renfoncement sous l'ailette ; et c) remplir le renfoncement d'un matériau (209) gravable sélectivement par rapport à l'oxyde de silicium.

    摘要翻译： 该方法包括从半导体层的表面形成在半导体层（101）中限定半导体鳍（107）并且一直延伸到半导体支撑（105）的表面的沟槽。 对位于翅片下方的氧化硅层（103）的一部分的侧面进行蚀刻以在翅片下方形成凹部。 凹部填充有材料，例如 氮化物，可在氧化硅上选择性蚀刻，其中该材料具有比氧化硅更大的介电常数。 沟槽一直延伸到支撑的中间水平。 对于由绝缘体上半导体（SOI）型结构形成的金属氧化物半导体（MOS）晶体管，还包括独立权利要求。

    MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD
    8.
    发明公开
    MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
    多DIELEKTISCHE的FinFET结构和工艺

    公开(公告)号：EP1787331A2

    公开(公告)日：2007-05-23

    申请号：EP05725829.5

    申请日：2005-03-18

    申请人： International Business Machines Corporation

    发明人： CLARK, William, F., Jr. ,  NOWAK, Edward, J.

    IPC分类号： H01L29/423

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

    摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics (502, 504) covering the fins (112, 113, 114) extending from the substrate (110). These fins have a central channel region and source (60) and drain (62) regions on opposite sides of the channel region. The thicker gate dielectrics (504) can comprise multiple layers of dielectric (200, 500) and the thinner gate dielectrics (502) can comprise less layers of dielectric (200). A cap (116) comprising a different material than the gate dielectrics can be positioned over the fins.