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13 条记录 (耗时 0.013 秒)

    A method for forming a transistor structure comprising a fin-shaped channel structure
    2.
    发明公开
    A method for forming a transistor structure comprising a fin-shaped channel structure 审中-公开
    Verfahren zur Herstellung einer Transistorstruktur mit einerflossenförmigenKanalstruktur

    公开(公告)号：EP3016143A1

    公开(公告)日：2016-05-04

    申请号：EP14191340.0

    申请日：2014-10-31

    申请人： IMEC VZW

    发明人： Collaert, Nadine ,  Eneman, Geert ,  Horiguchi, Naoto ,  Kim, Min-Soo ,  Rooyackers, Rita ,  Veloso, Anabela ,  Witters, Liesbeth

    IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66

    CPC分类号： H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    摘要： A method for forming a transistor structure comprising a fin-shaped channel structure, comprising:
    - providing a layer stack embedded laterally in STI structures;
    - recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion;
    - providing one or more protection layers on the upper portion of the layer stack;
    - after providing one or more protection layers, further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack;
    - removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other;
    wherein providing the layer stack comprises providing an etch stop layer at a position directly below the channel portion, such that the freestanding upper part of the layer stack comprises an etch stop layer at its lower surface after selectively removing the central portion.

    摘要翻译： 一种用于形成包括鳍状沟道结构的晶体管结构的方法，包括：提供在STI结构中横向嵌入的层堆叠; - 将STI结构凹陷到层堆叠附近，从而暴露层堆叠的上部，上部至少包括通道部分; - 在所述层堆叠的上部提供一个或多个保护层; - 在提供一个或多个保护层之后，进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分; - 去除层堆叠的中心部分，导致层堆叠的独立上部和下部在物理上彼此分离; 其中提供层堆叠包括在通道部分正下方的位置处提供蚀刻停止层，使得层堆叠的独立上部在选择性地去除中心部分之后在其下表面处包含蚀刻停止层。

    Heterosection tunnel field-effect transistor (TFET)
    3.
    发明公开
    Heterosection tunnel field-effect transistor (TFET) 审中-公开
    异质晶体管（TFET）

    公开(公告)号：EP2993696A1

    公开(公告)日：2016-03-09

    申请号：EP14183296.4

    申请日：2014-09-02

    申请人： IMEC VZW

    发明人： Verhulst, Anne S. ,  Pourtois, Geoffrey ,  Rooyackers, Rita

    IPC分类号： H01L29/66 ,  H01L29/739

    摘要： A TFET device is disclosed comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

    摘要翻译： 公开了一种TFET装置，其包括在源极区域和沟道区域之间的至少一个异源区域。 所述至少一个杂交具有低介电常数和低于10nm的厚度。 此外，可以在至少一个异源区域和通道区域之间加入口袋区域和另一杂交。

    Method for fabricating a semiconductor device and the semiconductor device made thereof
    4.
    发明公开
    Method for fabricating a semiconductor device and the semiconductor device made thereof 审中-公开
    一种用于生产由一种半导体器件以及半导体器件的工艺

    公开(公告)号：EP2073256A1

    公开(公告)日：2009-06-24

    申请号：EP08153499.2

    申请日：2008-03-28

    申请人： Interuniversitair Microelektronica Centrum vzw (IMEC) ,  STMicroelectronics (Crolles 2) SAS

    发明人： Lenoble, Damien ,  Rooyackers, Rita

    IPC分类号： H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/66795 ,  H01L29/7854

    摘要： The present invention is related to a method for fabricating a semiconductor device, said method comprising the following subsequent steps:
    - providing a substrate comprising a semiconductor material,
    - patterning at least one fin in said substrate, said fin comprising a top surface, at least one sidewall surface, and at least one corner,
    - creating a supersaturation of point defects in the at least one fin, then
    - annealing and subsequently cooling down the at least one fin such that semiconductor atoms of the semiconductor material migrate via the point defects.

    摘要翻译： 本发明涉及一种用于制造半导体器件的方法，所述方法包括下列连续步骤： - 提供一基板，其包括半导体材料， - 图案化在所说基片的至少一个翼片，所述鳍状物包括顶面，至少， 一个侧壁表面上，并且至少一个角部， - 创建点缺陷的在所述至少一个鳍片，然后过饱和 - 退火并随后冷却所述至少一个翅片搜索那样的半导体材料的半导体原子经由点缺陷迁移。

    Method of manufacturing a vertical TFET
    7.
    发明公开
    Method of manufacturing a vertical TFET 有权
    Verfahren zur Herstellung eines vertikalen TFET

    公开(公告)号：EP2378557A1

    公开(公告)日：2011-10-19

    申请号：EP10160382.7

    申请日：2010-04-19

    申请人： IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

    发明人： Rooyackers, Rita ,  Leonelli, Daniele ,  Vandooren, Anne ,  Verhulst, Anne ,  Loo, Roger ,  De Gendt, Stefan

    IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267

    CPC分类号： H01L29/7391 ,  B82Y10/00 ,  H01L21/823885 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66356

    摘要： The present invention provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack (24) comprising a layer of channel material (34) with on top thereof a layer of sacrificial material (21), removing material from the stack (24) so as to form at least one nanowire (30) from the layer of channel material (34) and the layer of sacrificial material (21), and replacing the sacrificial material (21) in the at least one nanowire (30) by heterojunction material (41, 52). A method according to embodiments of the present invention is advantageous as it enables easy manufacturing of complementary TFETs.

    摘要翻译： 本发明提供一种用于制造至少一个纳米线隧道场效应晶体管（TFET）半导体器件的方法。 该方法包括提供包括沟道材料层（34）的堆叠（24），其顶部具有牺牲材料层（21），从堆叠（24）去除材料，以形成至少一个纳米线（30） 从所述通道材料层（34）和所述牺牲材料层（21）开始，并且通过异质结材料（41,42）代替所述至少一个纳米线（30）中的所述牺牲材料（21）。 根据本发明的实施例的方法是有利的，因为它能够容易地制造互补的TFET。

    Recursive spacer defined patterning
    8.
    发明公开
    Recursive spacer defined patterning 审中-公开
    Strukturierung mittels rekursiver Spacertechnik

    公开(公告)号：EP1764827A1

    公开(公告)日：2007-03-21

    申请号：EP05447285.7

    申请日：2005-12-19

    申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

    发明人： DeGroote, Bart ,  Rooyackers, Rita

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/027

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention relates to a method for the patterning of a plurality of fins in a MugFET device. The present invention is achieved by depositing at least one temporary pattern using photolithography. Further processing steps are a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very high density of fins can be achieved. The distance between the fins is no longer determined by photolithography (only used to define the temporary pattern which is removed in further processing) but by the thickness of the conformal layer (all fins are defined by spacers). Additionally an improved line edge roughness will be achieved for the fins using the method of the invention.

    摘要翻译： 本发明涉及一种用于在MugFET器件中图形化多个翅片的方法。 本发明通过使用光刻沉积至少一个临时图案来实现。 进一步的处理步骤是沉积保形层和间隔物限定图案化保形层的组合，使得可以实现非常高密度的散热片。 翅片之间的距离不再由光刻法确定（仅用于限定在进一步处理中除去的临时图案），而是通过保形层的厚度（所有散热片由间隔物限定）。 另外，使用本发明的方法，对翅片将实现改进的线边缘粗糙度。

    A method for manufacturing a transistor device and associated device
    9.
    发明授权
    A method for manufacturing a transistor device and associated device 有权
    一种制造晶体管器件和相关器件的方法

    公开(公告)号：EP2887399B1

    公开(公告)日：2017-08-30

    申请号：EP14151285.5

    申请日：2014-01-15

    申请人： IMEC

    发明人： Rooyackers, Rita ,  Collaert, Nadine ,  Eneman, Geert

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

    CPC分类号： H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

    摘要： A method for manufacturing a transistor device, the method comprising a. providing a plurality of parallel nanowires on a substrate; b. providing a dummy gate structure over a central portion of the parallel nanowires; c. epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; d. providing a filler layer around and on top of the dummy gate structure and the extension portions; e. removing the dummy gate structure, in order to create a gate trench, exposing the central portion of the parallel nanowires; f. providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; g. thinning the parallel nanowires, thereby creating free space in between the nanowires and the spacer structures; h. selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and the respective extension portions.

    摘要翻译： 一种制造晶体管器件的方法，该方法包括a。 在衬底上提供多个平行纳米线; 湾 在平行纳米线的中心部分上提供伪栅极结构; C。 在中心部分外部选择性地在平行纳米线上外延生长第二材料的延伸部分; d。 在伪栅极结构和延伸部分的周围和顶部上提供填充层; 即 去除伪栅极结构，以便形成栅极沟槽，暴露平行纳米线的中心部分; F。 在栅极沟槽的侧壁上提供间隔物结构以限定最终的栅极沟槽; G。 使平行纳米线变薄，从而在纳米线和间隔件结构之间形成自由空间; H。 在平行纳米线上或周围选择性生长量子阱层，至少部分地填充自由空间，从而提供量子阱层和相应延伸部分之间的连接。