公开(公告)号：EP3311417A1

公开(公告)日：2018-04-25

申请号：EP15895823.1

申请日：2015-06-19

申请人： Intel Corporation

发明人： GLASS, Glenn A. ,  KEYS, Patrick H. ,  KENNEL, Harold W. ,  MEHANDRU, Rishabh ,  MURTHY, Anand S. ,  JAMBUNATHAN, Karthik

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.

公开(公告)号：EP3235007A1

公开(公告)日：2017-10-25

申请号：EP14908566.4

申请日：2014-12-17

申请人： Intel Corporation

发明人： DEWEY, Gilbert ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy ,  GHANI, Tahir ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S. ,  KENNEL, Harold W. ,  GLASS, Glenn A.

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

摘要： An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种器件，该器件包括：包括掺杂沟槽材料的沟槽，所述掺杂沟槽材料具有：（a）（i）第一体晶格常数和（a）（ii）III-V族材料和IV族材料中的至少一种 ; （b）（ii）第二体晶格常数和（b）（ii）III-V族材料和IV族材料中的至少一种的翅片材料; 在所述沟槽内并直接接触所述鳍状物的底表面的阻挡层，所述阻挡层包括具有第三体晶格常数的阻挡层材料; 其中（a）所述沟槽具有至少1.5:1的纵横比（深度与宽度），并且（b）所述阻挡层具有不高于所述阻挡层材料的临界厚度的高度。 这里描述了其他实施例。

公开(公告)号：EP3437137A1

公开(公告)日：2019-02-06

申请号：EP16897413.7

申请日：2016-04-01

申请人： INTEL Corporation

发明人： MOHAPATRA, Chandra S. ,  GLASS, Glenn A. ,  KENNEL, Harold W. ,  MURTHY, Anand S. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  MA, Sean T. ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

公开(公告)号：EP3123514A1

公开(公告)日：2017-02-01

申请号：EP14886927.4

申请日：2014-03-28

申请人： Intel Corporation

发明人： LE, Van H. ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack T. ,  PILLARISETTY, Ravi ,  RACHMADY, Willy ,  KENNEL, Harold W.

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/155 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，包括：第一外延层，耦合到衬底，具有第一晶格常数; 第二外延层，在第一层上，具有第二晶格常数; 第三外延层，与第二层的上表面接触，具有不等于第二晶格常数的第三晶格常数; 以及在所述第三层上的包括沟道区的外延器件层; 其中（a）所述第一层被松弛并且包括缺陷，（b）所述第二层是压缩应变的，并且所述第三层是拉伸应变的，以及（c）所述第一层，第二层，第三层和所述器件层都包括在沟槽 。 本文描述了其它实施例。

公开(公告)号：EP4300591A1

公开(公告)日：2024-01-03

申请号：EP23173199.3

申请日：2023-05-12

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  ZIGONEANU, Imola ,  DEWEY, Gilbert ,  JAHAGIRDAR, Anant H. ,  KENNEL, Harold W. ,  PATEL, Pratik ,  MURTHY, Anand ,  CHOI, Chi-Hing ,  KOBRINSKY, Mauro J. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm 2 .

公开(公告)号：EP3050091B1

公开(公告)日：2019-04-10

申请号：EP13894881.5

申请日：2013-09-27

申请人： Intel Corporation

发明人： PILLARISETTY, Ravi ,  DASGUPTA, Sansaptak ,  GOEL, Niti ,  LE, Van H. ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  RACHMADY, Willy ,  KAVALIEROS, Jack T. ,  CHU-KUNG, Benjamin ,  KENNEL, Harold W. ,  CEA, Stephen M. ,  CHAU, Robert S.

IPC分类号： H01L21/8234 ,  H01L29/267 ,  H01L29/165 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16

公开(公告)号：EP3238266A1

公开(公告)日：2017-11-01

申请号：EP14909240.5

申请日：2014-12-23

申请人： INTEL Corporation

发明人： KENNEL, Harold W. ,  METZ, Matthew V. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  KAVALIEROS, Jack T. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/785 ,  H01L29/78681

摘要： Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

摘要翻译： 描述了包括包括第一III-V半导体合金的子鳍和包括第二III-V半导体合金的沟道的半导体器件。 在一些实施例中，半导体器件包括衬底，该衬底包括由至少两个沟槽侧壁限定的沟槽，其中第一III-V半导体合金沉积在沟槽内的衬底上，并且第二III-V半导体合金外延生长在第一 III-V半导体合金。 在一些实施例中，第一III-V半导体合金与第二III-V半导体合金之间的导带偏移大于或等于约0.3电子伏特。 还描述了制造这种半导体器件的方法和包括这种半导体器件的计算设备。

公开(公告)号：EP4109553A1

公开(公告)日：2022-12-28

申请号：EP22180459.4

申请日：2022-06-22

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  BOMBERGER, Cory ,  DEWEY, Gilbert ,  MURTHY, Anand S. ,  KOBRINSKY, Mauro ,  SHAH, Rushabh ,  CHOI, Chi-Hing ,  KENNEL, Harold W. ,  SAADAT, Omair ,  ONI, Adedapo ,  HARATIPOUR, Nazila ,  GHANI, Tahir

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

摘要： Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：EP3314667A1

公开(公告)日：2018-05-02

申请号：EP15897305.7

申请日：2015-06-27

申请人： INTEL Corporation

发明人： KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  GHANI, Tahir ,  KENNEL, Harold W.

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/2258 ,  H01L21/8258 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66803

摘要： Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.

公开(公告)号：EP3314660A1

公开(公告)日：2018-05-02

申请号：EP15896504.6

申请日：2015-06-23

申请人： Intel Corporation

发明人： MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  GHANI, Tahir ,  RACHMADY, Willy ,  KAVALIEROS, Jack T. ,  DEWEY, Gilbert ,  METZ, Matthew V. ,  KENNEL, Harold W.

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

摘要： Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.