公开(公告)号：EP0207266A2

公开(公告)日：1987-01-07

申请号：EP86106541.5

申请日：1986-05-14

申请人： Licentia Patent-Verwaltungs-GmbH

发明人： Herzog, Hans J. ,  Jorke, Helmut ,  Kibbel, Horst

IPC分类号： H01L29/14

CPC分类号： H01L29/155 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02576 ,  Y10S148/04 ,  Y10S148/058 ,  Y10S148/072 ,  Y10S148/132 ,  Y10S148/16 ,  Y10S438/918 ,  Y10S438/938

摘要： Die Erfindung betrifft Halbleiter-Supergitter, insbesondere Si-SiGe-Supergitter, in denen die Elektronenbeweglichkeit erheblich erhöht wird. Dieses wird erreicht durch eine selektive Sb-Dotierung der SiGe-Halbleiterschichten des Supergitters.

摘要翻译： 本发明涉及一种半导体超晶格，其中电子迁移率显着增加，特别是硅的SiGe超晶格。 这是由超晶格的硅锗半导体层的选择性的Sb掺杂实现。

公开(公告)号：EP0567936A1

公开(公告)日：1993-11-03

申请号：EP93106586.6

申请日：1993-04-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yuan, Han-Tzong ,  Kim, Tae S. ,  Plumton, Donald L. ,  Morris, Francis J.

IPC分类号： H01L29/76 ,  H01L29/207 ,  H01L21/205

CPC分类号： H01L29/66454 ,  H01L29/207 ,  H01L29/66924 ,  H01L29/7722 ,  Y10S148/04

摘要： This is a method of forming a vertical GaAs transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. Due to the small diffusibility of carbon in GaAs, the buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

摘要翻译： 这是形成垂直GaAs晶体管器件的方法。 该方法包括：形成n型源极层12; 形成p +碳掺杂栅极层14; 从栅极层形成栅极结构; 以及在所述栅极结构上形成n型漏极层16以提供掩埋的碳掺杂栅极结构。 由于GaAs在GaAs中的扩散性很小，埋入碳掺杂的栅结构提供了非常小的器件，具有良好的导通电阻，结电容，栅极电阻和栅极驱动电压。 还公开了其它装置和方法。

公开(公告)号：EP0207266B1

公开(公告)日：1990-03-21

申请号：EP86106541.5

申请日：1986-05-14

申请人： Licentia Patent-Verwaltungs-GmbH

发明人： Herzog, Hans J. ,  Jorke, Helmut ,  Kibbel, Horst

IPC分类号： H01L29/14

CPC分类号： H01L29/155 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02576 ,  Y10S148/04 ,  Y10S148/058 ,  Y10S148/072 ,  Y10S148/132 ,  Y10S148/16 ,  Y10S438/918 ,  Y10S438/938

公开(公告)号：EP0076105A2

公开(公告)日：1983-04-06

申请号：EP82305023.2

申请日：1982-09-23

申请人： FUJITSU LIMITED

发明人： Goto, Hiroshi

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L29/08

CPC分类号： H01L29/72 ,  H01L21/033 ,  H01L21/28512 ,  H01L29/42304 ,  Y10S148/01 ,  Y10S148/04

摘要： A method of producing a bipolar transistor comprises the steps of forming a base region (41), forming a high-melting-point metal layer (42) of a base electrode on the base region (41), forming a first insulating layer (43) on the metal layer (42), and selectively etching the first insulating layer (43) and the metal layer (42) to form an opening (45). A second insulating layer (46) is formed on the sides of the first insulating layer (43) and the metal layer (42) within the opening (45), the second insulating layer (46) defining an emitter-providing region. impurities are introduced into the base region (41) by using the second insulating layer (43) as a mask to form an emitter region (49). An emitter electrode (51) and the base electrode (42) are arranged in a like multilayer structure.

摘要翻译： 制造双极晶体管的方法包括以下步骤：形成基区（41）;在基区（41）上形成基极的高熔点金属层（42）;形成第一绝缘层（43） ）沉积在金属层（42）上，并选择性地蚀刻第一绝缘层（43）和金属层（42）以形成开口（45）。 在开口（45）内的第一绝缘层（43）和金属层（42）的侧面上形成第二绝缘层（46），第二绝缘层（46）限定发射极提供区。 通过使用第二绝缘层（43）作为掩模将杂质引入到基极区域（41）中以形成发射极区域（49）。 发射极电极（51）和基极电极（42）以类似的多层结构排列。

公开(公告)号：EP0651076B1

公开(公告)日：1999-08-11

申请号：EP94115744.8

申请日：1994-10-06

申请人： International Business Machines Corporation

发明人： Cabral, Cyril, Jr. ,  Clevenger, Lawrence Alfred ,  d'Heurle, Francois Max ,  Harper, James McKell Edwin ,  Mann, Randy William ,  Miles, Glen Lester ,  Rakowski, Donald Walter Douglas

IPC分类号： C30B1/02 ,  C30B1/00 ,  H01L21/285

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665 ,  Y10S148/04 ,  Y10S148/147

摘要： The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：EP0622834A2

公开(公告)日：1994-11-02

申请号：EP94102414.3

申请日：1994-02-17

申请人： International Business Machines Corporation

发明人： Brady, Frederick T. ,  Edenfeld, Arthur ,  Haddad, Nadim F.

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L29/784

CPC分类号： H01L29/66772 ,  H01L21/26506 ,  H01L29/78612 ,  Y10S148/04

摘要： SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating an advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improve radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant a neutral impurity ion such as krypton, xenon or germanium into the device (10) to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.

公开(公告)号：EP0207266A3

公开(公告)日：1987-03-18

申请号：EP86106541

申请日：1986-05-14

申请人： Licentia Patent-Verwaltungs-GmbH

发明人： Herzog, Hans J. ,  Jorke, Helmut ,  Kibbel, Horst

IPC分类号： H01L29/14

CPC分类号： H01L29/155 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02576 ,  Y10S148/04 ,  Y10S148/058 ,  Y10S148/072 ,  Y10S148/132 ,  Y10S148/16 ,  Y10S438/918 ,  Y10S438/938

公开(公告)号：EP0844653A3

公开(公告)日：2000-01-12

申请号：EP97120329.4

申请日：1997-11-20

申请人： Hughes Electronics Corporation

发明人： Nguyen, Chanh N. ,  Wilson, Robert G.

IPC分类号： H01L21/322 ,  H01L21/265

CPC分类号： H01L21/26586 ,  H01L21/2654 ,  H01L21/3228 ,  Y10S148/04 ,  Y10S438/918 ,  Y10S438/919

摘要： The number of surface defects in semiconductor materials having a volatile species, particularly group-III nitride-based semiconductor devices, are reduced by first implanting species atoms (11) into the semiconductor sample (12) to fill some of the surface layer (18) species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample (12) to repair broken bonds and crystalline defects and to move implanted species atoms (11) from interstitial to substitutional sites. An optional third step deposits a dummy layer (20) on the sample surface (16) prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer (18) than is attainable without the dummy layer (20) and to inhibit species atoms (11) from leaving the sample (12) during high-temperature processing steps that follow.

公开(公告)号：EP0844653A2

公开(公告)日：1998-05-27

申请号：EP97120329.4

申请日：1997-11-20

申请人： HE HOLDINGS, INC. dba HUGHES ELECTRONICS

发明人： Nguyen, Chanh N. ,  Wilson, Robert G.

IPC分类号： H01L21/322 ,  H01L21/265

CPC分类号： H01L21/26586 ,  H01L21/2654 ,  H01L21/3228 ,  Y10S148/04 ,  Y10S438/918 ,  Y10S438/919

摘要： The number of surface defects in semiconductor materials having a volatile species, particularly group-III nitride-based semiconductor devices, are reduced by first implanting species atoms (11) into the semiconductor sample (12) to fill some of the surface layer (18) species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample (12) to repair broken bonds and crystalline defects and to move implanted species atoms (11) from interstitial to substitutional sites. An optional third step deposits a dummy layer (20) on the sample surface (16) prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer (18) than is attainable without the dummy layer (20) and to inhibit species atoms (11) from leaving the sample (12) during high-temperature processing steps that follow.

摘要翻译： 表面缺陷的在半导体材料中具有的挥发性物质，特别是III族氮化物基半导体器件的个数，通过首先注入物种原子（11）到半导体样品（12）减少到填补部分表面层（18） 通过生长和器件制造工艺创建物种空缺，然后快速热退火的样品（12）来修复断裂的键和晶体缺陷，并从间质植入物种原子（11）移动到取代位置。 （可选的第三步骤沉积物的虚设样品表面（16）在植入前对层（20），使得能够植入轮廓确实地在表面层（18）物种原子的更高的密度比是不使用虚设层可达到 20），并从在高温处理步骤并遵循离开样品（12）抑制物种原子（11）。

公开(公告)号：EP0622834A3

公开(公告)日：1998-02-11

申请号：EP94102414.3

申请日：1994-02-17

申请人： International Business Machines Corporation

发明人： Brady, Frederick T. ,  Edenfeld, Arthur ,  Haddad, Nadim F.

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L29/784

CPC分类号： H01L29/66772 ,  H01L21/26506 ,  H01L29/78612 ,  Y10S148/04

摘要： SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating an advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improve radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant a neutral impurity ion such as krypton, xenon or germanium into the device (10) to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.

摘要翻译： SOI（绝缘体上硅）技术已被广泛用作制造先进集成电路的有希望的方法，因为其优于体硅电路，例如更快的速度和更好的辐射耐受性。 SOI的一个缺点是寄生双极性诱发闭锁/击穿电压电平严重限制了SOI电路和器件可以工作的最大电源电压。 当寄生器件导通时，通过改变栅极偏置，不能关闭SOI晶体管。 所描述的是一种方法，其中发生该效应的工作电压显着增加，从而允许在合理的电源电压下进行电路操作。 该方法是将诸如氪，氙或锗的中性杂质离子注入器件（10）以形成离子散射中心。 杂质原子的大小必须远大于硅原子的大小。 产生散射中心的尺寸差异。