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    Method of producing a bipolar transistor
    3.
    发明公开
    Method of producing a bipolar transistor 失效
    制造双极晶体管的方法

    公开(公告)号：EP0076105A2

    公开(公告)日：1983-04-06

    申请号：EP82305023.2

    申请日：1982-09-23

    申请人： FUJITSU LIMITED

    发明人： Goto, Hiroshi

    IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L29/08

    CPC分类号： H01L29/72 ,  H01L21/033 ,  H01L21/28512 ,  H01L29/42304 ,  Y10S148/01 ,  Y10S148/04

    摘要： A method of producing a bipolar transistor comprises the steps of forming a base region (41), forming a high-melting-point metal layer (42) of a base electrode on the base region (41), forming a first insulating layer (43) on the metal layer (42), and selectively etching the first insulating layer (43) and the metal layer (42) to form an opening (45). A second insulating layer (46) is formed on the sides of the first insulating layer (43) and the metal layer (42) within the opening (45), the second insulating layer (46) defining an emitter-providing region. impurities are introduced into the base region (41) by using the second insulating layer (43) as a mask to form an emitter region (49). An emitter electrode (51) and the base electrode (42) are arranged in a like multilayer structure.

    摘要翻译： 制造双极晶体管的方法包括以下步骤：形成基区（41）;在基区（41）上形成基极的高熔点金属层（42）;形成第一绝缘层（43） ）沉积在金属层（42）上，并选择性地蚀刻第一绝缘层（43）和金属层（42）以形成开口（45）。 在开口（45）内的第一绝缘层（43）和金属层（42）的侧面上形成第二绝缘层（46），第二绝缘层（46）限定发射极提供区。 通过使用第二绝缘层（43）作为掩模将杂质引入到基极区域（41）中以形成发射极区域（49）。 发射极电极（51）和基极电极（42）以类似的多层结构排列。

    Process for producing an interconnection structure of a semiconductor device
    6.
    发明公开
    Process for producing an interconnection structure of a semiconductor device 失效
    用于生产半导体器件的互连结构的方法

    公开(公告)号：EP0154419A3

    公开(公告)日：1988-05-04

    申请号：EP85300829

    申请日：1985-02-08

    申请人： FUJITSU LIMITED

    发明人： Tuchiya, Takahiro ,  Tukuda, Kazuaki Room 2501 Fujitsu-Aobasai-Ryo ,  Takada, Tadakazu ,  Goto, Hiroshi

    IPC分类号： H01L21/90 ,  H01L23/52

    CPC分类号： H01L23/53295 ,  H01L21/76819 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Planarization of an insulating layer (10) formed on a lower wiring layer (8-6, 8-4, 8-2) and having steps at the shoulders of the wiring patterns, can be attained. On a lower wiring layer (8-6, 8-4, 8-2), a lower insulating layer (10) is formed and a heat resistive material (16) is coated over the lower insulating layer, to form a substantially planar top surface and to fill cavities (22) appearing in the surface of the , lower insulating layer with material (16). Then, etching is carried out to preserve the profile of the surface of the coating layer (16) and to remove the coating layer at portions (18) where through-holes (26) are to be formed. The cavities (22) are still filled with the material (16) after etching. An upper insulating layer (24) is deposited on the exposed lower insulating layer (10) and the remaining part of the coating layer (16). Through-holes (26) and an upper wiring layer (28) are formed. Thus, the upper wiring layer (28) has no contact with the remaining part of the coating layer (16) and the remaining part of the coating layer is never externally exposed.

    Process for fabricating a self-aligned bipolar transistor
    7.
    发明公开
    Process for fabricating a self-aligned bipolar transistor 失效
    制造双极晶体管selbtsausrichtenden的方法。

    公开(公告)号：EP0199497A2

    公开(公告)日：1986-10-29

    申请号：EP86302631.6

    申请日：1986-04-09

    申请人： FUJITSU LIMITED

    发明人： Hideshima, Osamu ,  Goto, Hiroshi

    IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/265 ,  H01L29/10

    CPC分类号： H01L29/66272 ,  H01L21/0337 ,  H01L29/42304

    摘要： Using a single mask pattern (36,37) on a semiconductor substracte (31), a doped base contact region (39) adjacent the surface of the.substrate, a buried insulating region (38) below the base contact region, and an insulating layer (40) on the base contact region are formed. Optionally, a metal or metal silicide base-electrode-taking-out is formed on the base contact region. Doped emitter (44) and intrinsic base (41) regions are formed below the mask pattern. A collector region (33) is defined by the base contact region and the buried insulating layer to be therebetween i.e. below the mask pattern. Hence, the bipolar transistor formed thereby has a size which is no larger than necessary, thereby reducing the collector-base capacitance, the base resistance, and the size of the device.

    Process for producing an interconnection structure of a semiconductor device
    8.
    发明公开
    Process for producing an interconnection structure of a semiconductor device 失效
    Verfahren zum Herstellen einer Verbindungsstruktur von einer Halbleiteranordnung。

    公开(公告)号：EP0154419A2

    公开(公告)日：1985-09-11

    申请号：EP85300829.0

    申请日：1985-02-08

    申请人： FUJITSU LIMITED

    发明人： Tuchiya, Takahiro ,  Tukuda, Kazuaki Room 2501 Fujitsu-Aobasai-Ryo ,  Takada, Tadakazu ,  Goto, Hiroshi

    IPC分类号： H01L21/90 ,  H01L23/52

    CPC分类号： H01L23/53295 ,  H01L21/76819 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Planarization of an insulating layer (10) formed on a lower wiring layer (8-6, 8-4, 8-2) and having steps at the shoulders of the wiring patterns, can be attained. On a lower wiring layer (8-6, 8-4, 8-2), a lower insulating layer (10) is formed and a heat resistive material (16) is coated over the lower insulating layer, to form a substantially planar top surface and to fill cavities (22) appearing in the surface of the , lower insulating layer with material (16). Then, etching is carried out to preserve the profile of the surface of the coating layer (16) and to remove the coating layer at portions (18) where through-holes (26) are to be formed. The cavities (22) are still filled with the material (16) after etching. An upper insulating layer (24) is deposited on the exposed lower insulating layer (10) and the remaining part of the coating layer (16). Through-holes (26) and an upper wiring layer (28) are formed. Thus, the upper wiring layer (28) has no contact with the remaining part of the coating layer (16) and the remaining part of the coating layer is never externally exposed.

    摘要翻译： 可以实现在下布线层（8-6,8-4,8-​​2）上形成并且在布线图案的肩部具有台阶的绝缘层（10）的平面化。 在下布线层（8-6,8-4,8-​​2）上，形成下绝缘层（10）并且在下绝缘层上涂覆耐热材料（16），以形成基本平坦的顶部 并用材料（16）填充出现在下绝缘层的表面中的空腔（22）。 然后，进行蚀刻以保持涂层（16）的表面的轮廓，并在要形成通孔（26）的部分（18）处去除涂层。 蚀刻后，空腔（22）仍然填充有材料（16）。 在暴露的下绝缘层（10）和涂层（16）的其余部分上沉积上绝缘层（24）。 形成通孔（26）和上部布线层（28）。 因此，上布线层（28）不与涂层（16）的剩余部分接触，并且涂层的其余部分不会从外部暴露。

    Method of producing a semiconductor device having isolation regions between elements
    9.
    发明公开
    Method of producing a semiconductor device having isolation regions between elements 失效
    制造与单元之间的隔离区域的半导体器件的方法。

    公开(公告)号：EP0116789A1

    公开(公告)日：1984-08-29

    申请号：EP83307977.5

    申请日：1983-12-23

    申请人： FUJITSU LIMITED

    发明人： Goto, Hiroshi

    IPC分类号： H01L21/76

    CPC分类号： H01L21/763 ,  H01L21/76 ,  H01L21/76224

    摘要： A semiconductor device of transistors, each of which is surrounded with a field oxide film (7), uses a dielectric isolation structure of a groove filled with an insulating material (15) instead of a PN junction isolation stucture. The field oxide film (7) is formed by selectively oxidizing an epitaxial layer (3), then the groove extending through the epitaxial layer (3) and a buried layer (2) is formed. After the surface of the groove is covered with an insulating film, e.g., a thermal oxide film (14) by oxidizing the surface, the groove is filled with the filler material (15).

    摘要翻译： 晶体管的半导体器件中，每个的所有其与场氧化膜 - （7）所包围，在使用绝缘材料（15）填充有槽而不是一个PN结隔离stucture的电介质隔离结构。 场氧化物膜 - （7）由外延层的选择性氧化（3），则该槽通过所述外延层（3）和埋入层（2）延伸的是形成。 凹槽的表面上的绝缘电影覆盖有后，E. G.，热氧化物膜 - （14）的表面氧化，槽填充有填充材料（15）。

    A method of producing a semiconductor device
    10.
    发明公开
    A method of producing a semiconductor device 失效
    Verfahren zur Herstellung einer Halbleitervorrichtung。

    公开(公告)号：EP0070499A2

    公开(公告)日：1983-01-26

    申请号：EP82106245.2

    申请日：1982-07-13

    申请人： FUJITSU LIMITED

    发明人： Goto, Hiroshi

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66272 ,  H01L21/32134

    摘要： The present invention relates to a method of producing a bipolar type semiconductor device. A method of producing semiconductor device of the present invention comprises the following processes:


    an insulating layer consisting of an oxide film of a semiconductor substrate or layer is formed on said silicon semiconductor substrate or layer having the first conductivity type;
    a polycrystalline semiconductor layer is formed on said insulating layer;
    a mask layer is formed on said polycrystalline semiconductor layer;
    a first base region is formed on said semiconductor substrate or layer by introducing the impurity of the second conductivity type through said polycrystalline semiconductor layer;
    the polycrystalline semiconductor layer under said mask layer is removed;
    an aperture is formed on said insulating layer with the remaining polycrystalline semiconductor layer or its oxide film used as the mask;
    a second base region which is placed in contact with said first base region is formed by introducing the second conductivity type impurity into said semiconductor substrate or layer through said aperture;
    and moreover the first conductivity type emitter region is formed within said second base region through said aperture.

    摘要翻译： 本发明涉及一种制造双极型半导体器件的方法。 本发明的半导体器件的制造方法包括：在具有第一导电型的硅半导体衬底或层上形成由半导体衬底或层的氧化物膜构成的绝缘层;多晶半导体层 形成在所述绝缘层上; ...在所述多晶半导体层上形成掩模层;通过所述多晶半导体层引入所述第二导电类型的杂质，在所述半导体衬底或层上形成第一基极区域; 除去所述掩模层下面的半导体层;在所述绝缘层上形成孔，其余的多晶半导体层或其氧化物膜用作掩模;形成与所述第一基极区域接触的第二基极区域 通过将第二导电类型杂质引入所述半导体 或通过所述孔径的衬底或层; ...并且此外，所述第一导电类型发射极区域通过所述孔形成在所述第二基极区域内。