公开(公告)号：EP1292975B1

公开(公告)日：2007-03-21

申请号：EP01945456.0

申请日：2001-06-15

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： AUBERTON-HERVE, André

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The invention concerns a method for making substrates, in particular for optics, electronics, or optoelectronics, comprising an operation which consists in bonding a useful element (10, 16) of a first material on the surface of a support (2), comprising a second material. The invention is characterised in that: it further comprises an operation which consists in depositing an amorphous material (3), on the surface of the support (2), formed with the second material and designed to receive the element consisting of the first material or on the surface of the useful element formed with the first material and designed to be bonded on the support (2); and the second material is less noble than the first material. The invention also concerns a method for making substrates, in particular for optics, electronics or optoelectronics, comprising an operation which consists in bonding a useful element (10) of a first material on a surface of a support (2), comprising a second material. The method is characterised in that the useful element (10) or the support (2) comprises a polycrystalline material at least on its surface designed to be bonded, and it further comprises, prior to the bonding operation, an operation which consists in forming a layer of amorphous material (2), on the surface or surfaces comprising the polycrystalline material.

公开(公告)号：EP1344246B1

公开(公告)日：2007-01-24

申请号：EP01997835.2

申请日：2001-11-26

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： LETERTRE, Fabrice ,  GHYSELEN, Bruno

IPC分类号： H01L21/20

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0445 ,  H01L21/76254 ,  H01L29/1608

摘要： The invention concerns a method for making substrates, in particular for optics, electronics or optoelectronics. The method comprises steps which consist in: transferring a seed layer (2) onto a support (12) by molecular adhesion at the bonding interface; epitaxial growth of a useful layer (16) on the seed layer, and applying stresses to produce removal of the formed assembly from the seed layer (2) and the useful layer (16) relative to the support (12) at the bonding interface.

公开(公告)号：EP1734571A1

公开(公告)日：2006-12-20

申请号：EP05291261.5

申请日：2005-06-10

申请人： S.O.I.TEC. Silicon on Insulator Technologies S.A.

发明人： Bras, Marlene

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a method for calibrating thermal processing equipment comprising a heating device and which is used for heat treatment of a multilayer substrate. To be able to optimize the calibration method while at the same time using cheaper material, the inventive method is characterized in comprising the steps: providing a test substrate with a different structure compared to the multilayer substrate, thermal processing of the test substrate using a set of thermal process parameters to thereby obtain a layer on the test substrate with a thickness profile, comparing the thickness profile with a predetermined thickness profile of a calibration layer on a calibration test substrate and amending the set of thermal process parameters such that the heating device is adapted to compensate the differences between the thickness profile and the predetermined thickness profile, wherein the predetermined thickness profile of the calibration layer on the calibration test substrate corresponds to an even thickness profile of a layer on a multilayer substrate both obtained with the same set of predetermined process conditions or to thermal process conditions for which reduced slip lines and/or reduced wafer deformation have been observed on the multilayer substrate. The invention also relates to a method for creating a calibration thickness profile and to a calibration test substrate comprising a thermally formed layer on one of its main surfaces with a predetermined thickness profile.

摘要翻译： 本发明涉及一种用于校准包括加热装置并且用于多层基板的热处理的热处理设备的方法。 为了能够优化校准方法同时使用更便宜的材料，本发明的方法的特征在于包括以下步骤：提供与多层基底相比具有不同结构的测试基板，使用一组测试基板进行热处理 的热处理参数，从而在测试基板上获得具有厚度分布的层，将厚度分布与校准测试基板上的校准层的预定厚度分布进行比较，并且修改该组热处理参数，使得加热装置为 适于补偿厚度分布和预定厚度分布之间的差异，其中校准测试基底上的校准层的预定厚度分布对应于多层基底上的层的均匀厚度分布，两者均用相同的一组预定 工艺条件或热处理条件 已经在多层基板上观察到减少滑移线和/或减小的晶片变形的离子。 本发明还涉及一种用于产生校准厚度分布的方法以及校准测试基底，其包括在其主表面之一上具有预定厚度分布的热成形层。

公开(公告)号：EP1723671A2

公开(公告)日：2006-11-22

申请号：EP05708800.7

申请日：2005-03-10

申请人： S.O.I.TEC. Silicon on Insulator Technologies S.A.

发明人： ALLIBERT, Frédéric ,  BRUNIER, François

IPC分类号： H01L23/544

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a first embodiment, the invention relates to a method for treating an electrically conductive working layer of a multilayer structure made from semiconductor materials, the structure including under said working layer an electrically insulating layer, said treatment being destined to constitute in said working layer at least one island surrounded by material of the electrically insulating layer, method including a wet chemical etching step of the working layer, method characterised in that prior to the wet etching step selective masking is realised on several regions of said working layer in order to constitute in this working layer several islands, each region masked from the layer corresponding to a respective island. The invention also proposes the application of such a method to the characterisation of the electrical properties of a structure, and an associated device.

公开(公告)号：EP1719179A1

公开(公告)日：2006-11-08

申请号：EP04714396.1

申请日：2004-02-25

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： DUPONT, Frédéric ,  CAYREFOURCQ, Ian

IPC分类号： H01L27/146 ,  H01L31/028 ,  H01L31/0368 ,  H01L31/18

CPC分类号： H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469

摘要： A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.

公开(公告)号：EP1429381A3

公开(公告)日：2006-10-04

申请号：EP03292888.9

申请日：2003-11-20

申请人： S.O.I.Tec Silicon on Insulator Technologies ,  Commisariat à l'énergie Atomique

发明人： Berne, Cecile, c/o SOITEC ,  Ghyselen, Bruno, c/o SOITEC ,  Lagahe, Chrystelle, c/o CEA ,  Thibaut, Maurice, c/o SOITEC

IPC分类号： H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76254

摘要： The present invention relates to a method for manufacturing of a material compound, in particular a heterogeneous or a non-heterogeneous material compound like a silicon-on-insulator (SOI)-material, comprising the steps of forming of a predetermined splitting area in a source substrate of a first material; attaching the source substrate to a handle substrate of a second material to form a source-handle-compound; and thermal annealing of the source substrate for a thermal splitting of the source substrate at the predetermined splitting area. It is the object of the present invention to provide a method of the above-mentioned type which can be easily carried out with a reduced process time and a very low risk of damage or destruction of the material to get a high quality of the split surface. This object is solved by a method of the above-mentioned type characterised in that the thermal annealing comprises a first annealing step of the source-handle-compound, wherein the first annealing step is stopped before a splitting of the source substrate; and a second annealing step of the source-handle-compound after the first annealing step, wherein the second annealing step is performed at a lower temperature than the first annealing step.

公开(公告)号：EP1697981A1

公开(公告)日：2006-09-06

申请号：EP03819093.0

申请日：2003-12-03

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： NEYRET, Eric ,  MALEVILLE, Christophe ,  ECARNOT, Ludovic

IPC分类号： H01L21/324 ,  H01L21/306

CPC分类号： H01L21/02052 ,  H01L21/324 ,  H01L21/76251

摘要： The present invention relates to a process for reducing the roughness of the free surface of a semiconductor wafer, said process comprising a single annealing step for smoothing said free surface, said single annealing step being carried out as a RTA under an atmosphere of pure argon, characterized in that before the RTA a chemical cleaning of the wafer surface is carried out so as to reduce the amount of preliminary pollutants on the wafer.

公开(公告)号：EP1639633A2

公开(公告)日：2006-03-29

申请号：EP04767314.0

申请日：2004-06-10

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： SCHWARZENBACH, Walter ,  WAECHTER, Jean-Marc

IPC分类号： H01L21/762

CPC分类号： H01L21/2007 ,  H01L21/324 ,  H01L21/76251

摘要： The invention relates to a thermal treatment method for stabilising a multilayer wafer formed from materials selected from semiconductor materials and comprising two wafers which are connected by means of a connecting interface. According to said method, the temperature is increased to an end-of-treatment temperature, said temperature increase being carried out with at least one constant stage.

公开(公告)号：EP1631984A1

公开(公告)日：2006-03-08

申请号：EP04767238.1

申请日：2004-06-03

申请人： S.O.I.Tec Silicon on Insulator Technologies ,  COMMISSARIAT A L'ENERGIE ATOMIQUE

发明人： AULNETTE, Cécile ,  BATAILLOU, Benoît ,  GHYSELEN, Bruno ,  MORICEAU, Hubert

IPC分类号： H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76254 ,  H01L21/76259

摘要： The invention relates to a method for obtaining a structure having at least one supporting substrate (3), an ultra-thin layer produced from a source substrate (1), particularly made of semiconductor material and optionally having an inserted layer. The inventive method comprises the following steps: a) adhering, by molecular adhesion, a supporting substrate (3) to the front face (10) of a source substrate (1) that has a fragilization area (12) which delimits a useful layer (13) to be transferred whose width is distinctly larger than that of said ultra-thin layer (130); b) removing said supporting substrate (3) from the remainder (14) of the source substrate (1) along said fragilization area (12) whereby obtaining an intermediate structure having at least said transferred useful layer (13) and said supporting substrate (3); c) thinning this transferred useful layer (13) until obtaining the ultra-thin layer. The invention is for use in the manufacture of substrates in the fields of electronics, optoelectronics or optics.

摘要翻译： 制造具有至少一个支撑基底和超薄层的半导体结构的方法。 该方法包括：贴合的支撑衬底的源基板，分离沿着弱化区的有用层，以获得在中间结构至少包括转移有用层和支撑基底，以及处理所述转移有用层，以获得对超薄层 支持基板。 源基片包括前表面和前表面下方的薄弱区域确实定义有用层，并且有用的层足够厚，以承受热处理而不形成缺陷在其中以便做到了能薄型化，以形成超薄层 ， 将所得的超薄层适用于在电子，光电子或光学领域的应用中使用。

公开(公告)号：EP1571705A3

公开(公告)日：2006-01-04

申请号：EP05290392.9

申请日：2005-02-22

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Le Vaillant, Yves Mathieu ,  Rayssac, Olivier ,  Fernandez, Christophe

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L2221/68318

摘要： L'invention concerne une réalisation d'une entité en matériau choisi parmi les matériaux semiconducteurs sur substrat.
Le procédé est mis en oeuvre à partir d'un substrat donneur et d'un substrat récepteur, le substrat récepteur comprenant en surface un ou plusieurs motifs en relief, le substrat donneur étant collé au substrat récepteur au niveau de ce ou ces motifs.
Une zone fragile est en outre présente dans le substrat donneur à une profondeur déterminée sous au moins un motif de sorte à définir une couche mince entre la zone fragile et l'interface de collage.
Le procédé comprend un apport d'énergie de sorte à :

― conserver le collage entre chaque motif et le substrat donneur ;
― détacher du substrat donneur une partie de la couche mince située au niveau de chaque motif, en rompant des liaisons dans la zone fragile et dans l'épaisseur de la couche mince, cette partie détachée formant l'entité.

L'invention comprend en outre une plaquette et une application du procédé à la réalisation de puces pour l'électronique, l'optique ou l'optoélectronique.