公开(公告)号：EP2225651A4

公开(公告)日：2012-07-25

申请号：EP08853698

申请日：2008-11-17

申请人： EMULEX DESIGN & MFG CORP

发明人： STEINMETZ JOSEPH H ,  KOMPELLA MURTHY ,  AYALASOMAYAJULA NARAYAN ,  SEBASTIAN DONIA

IPC分类号： G06F13/14 ,  G06F20060101 ,  G06F3/00 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42 ,  H04L29/08

CPC分类号： G06F13/4234 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0689 ,  G06F11/201 ,  G06F11/2089 ,  H04L67/1097

公开(公告)号：EP2411981A2

公开(公告)日：2012-02-01

申请号：EP10756723.2

申请日：2010-03-23

申请人： Micron Technology, Inc.

发明人： JEDDELOH, Joe, M.

IPC分类号： G11C7/00

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G11C5/063 ,  G11C11/4093 ,  Y02D10/14 ,  Y02D10/151

摘要： Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

公开(公告)号：EP2351036A1

公开(公告)日：2011-08-03

申请号：EP09824302.5

申请日：2009-10-27

申请人： MOSAID Technologies Incorporated

发明人： PYEON, Hong Beom ,  KIM, Jin-Ki ,  GILLINGHAM, Peter B.

IPC分类号： G11C11/34 ,  G11C7/22 ,  G11C8/18

CPC分类号： G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

公开(公告)号：EP2350847A2

公开(公告)日：2011-08-03

申请号：EP09752943.2

申请日：2009-10-27

申请人： Silicon Image, Inc.

发明人： RUBERG, Alan ,  LEE, Seung-jong ,  LEE, Hyung, Rok ,  SHIM, Daeyun ,  LEE, Dongyun ,  KIM, Sungjoon ,  MURTHY, Anu

IPC分类号： G06F13/42

CPC分类号： G11C7/1075 ,  G06F11/141 ,  G06F11/1443 ,  G06F13/1663 ,  G06F13/4234 ,  G11C5/066 ,  Y02D10/14 ,  Y02D10/151

摘要： A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

公开(公告)号：EP1688847B1

公开(公告)日：2011-05-04

申请号：EP05290245.9

申请日：2005-02-03

申请人： Texas Instruments Incorporated ,  TEXAS INSTRUMENTS FRANCE

发明人： Chauve, NIcolas ,  Zghal, Tarek ,  Leclercq, Maxime

IPC分类号： G06F13/42 ,  H01L25/065

CPC分类号： G06F13/4095 ,  G06F13/4234

公开(公告)号：EP2284719A3

公开(公告)日：2011-03-09

申请号：EP10179814.8

申请日：2000-10-16

申请人： Rambus Inc.

发明人： Horowitz, Mark A. ,  Barth, Richard M. ,  Hampel, Craig E. ,  Moncayo, Alfredo ,  Donnelly, Kevin S. ,  Zerbe, Jared L.

IPC分类号： G06F13/40

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topograpy dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the out-put driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristics in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is also adjusted in accordance with a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register. Parameter adjustment circuitry adjusts a control signal in accordance with the stored topography dependent parameter. An input buffer receives an input signal from a bus coupling the receiver to a transmitter of the input signal. The input buffer generates a first signal from the input signal by adjusting a parameter of the input signal in accordance with the control signal.

公开(公告)号：EP1595213A4

公开(公告)日：2010-09-08

申请号：EP04707003

申请日：2004-01-30

申请人： MICRON TECHNOLOGY INC

发明人： LOVETT SIMON J

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/00 ,  G11C7/10 ,  G11C11/40 ,  G11C11/406 ,  G11C11/413 ,  H01L20060101

CPC分类号： G06F13/4234 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/413

摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

公开(公告)号：EP1991930A1

公开(公告)日：2008-11-19

申请号：EP07705654.7

申请日：2007-02-20

申请人： ATI Technologies Inc.

发明人： MACRI, Joseph ,  MOREIN, Stephen, L. ,  LEE, Edward ,  CHEN, Lin

IPC分类号： G06F13/42

CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

公开(公告)号：EP1629393B1

公开(公告)日：2008-10-29

申请号：EP04752912.8

申请日：2004-05-20

申请人： Intel Corporation

发明人： VOGT, Pete, D. ,  ALEXANDER, James, S.

IPC分类号： G06F13/42

CPC分类号： G06F13/4234 ,  Y02D10/14 ,  Y02D10/151

摘要： Memory apparatus and methods utilize permuting status patterns. A memory agent may include a pattern generator capable of generating permuting status patterns. A system may include first and second memory agents that send data and permuting status patterns over the same link.

公开(公告)号：EP1683031B1

公开(公告)日：2008-05-07

申请号：EP04810427.7

申请日：2004-11-05

申请人： Intel Corporation

发明人： ELLIS, Robert

IPC分类号： G06F13/42

CPC分类号： G06F13/4234 ,  G06F13/4256 ,  H04L7/033

摘要： Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.