公开(公告)号：EP0760149A1

公开(公告)日：1997-03-05

申请号：EP95920943.0

申请日：1995-05-16

申请人： THOMSON-LCD

发明人： MAURICE, François

IPC分类号： G11C19 ,  G09G3

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/043 ,  G09G2310/0286 ,  G09G2320/0209

摘要： An LCD shift register having stages which use the Bootstrap effect and may only have three MIS transistors, as well as improvements to such a circuit having four or seven MIS transistors, are disclosed. The advantages are that the number of components used is reduced, the lifetime of the shift registers is extended, and it is possible to operate only with control signals having an amplitude 5 or 10 v lower than that of the output signals.

公开(公告)号：EP0615250A1

公开(公告)日：1994-09-14

申请号：EP94102865.6

申请日：1994-02-25

申请人： Lüder, Ernst, Prof. Dr.-Ing. habil.

发明人： Schleupen, Kai, Dipl.-Ing. ,  Lüder, Ernst, Prof. Dr.-Ing.

IPC分类号： G11C19/18 ,  G11C19/28 ,  G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/3674 ,  G09G2310/0286 ,  G11C19/184

摘要： Eine Schaltungsanordnung zur Ansteuerung von ketten- oder matrixförmig angeordneten Schaltelementen, die höchstens sieben Transistoren (T n1 , T n2 , T n3 , T n4 , T n5 , T n6 , T n7 ) und höchstens zwei Kapazitäten (C n1 , C nb ) aufweist und von vier gegen einander um 90° phasenverschobenen Taktsignalen (Φ₁, Φ₂, Φ₃, Φ₄) gesteuert ist, um eine möglichst hohe Fertigungsausbeute zu erzielen. Die Transistoren (T n5 , T n6 , T n7 ) zusammen mit einer Bootstrap-Kapazität (C nb ) bilden eine Ausgangsstufe (12). Mindestens ein weiterer Transistor bildet eine Lade und Entladestufe (II) für die Bootstrap-Kapazität.

摘要翻译： 一种用于驱动在链形式或以矩阵形成设置开关元件电路，其具有至多7个晶体管（TN1，TN2，Tn3的，TN4的Tn5 TN6，Tn7转）和至多两个电容（C N1，CNB），并且是 由四个时钟信号（PHI 1，披2，披3，披4）控制，通过90相对于相移彼此@，为了实现尽可能高的产率尽可能地制造。 晶体管（TN 5，TN6，Tn7转）与输出级的自举电容（CNB）形式（12）连接在一起。 至少一个另外的晶体管形成用于自举电容的充电和放电阶段（II）。

公开(公告)号：EP0203332A3

公开(公告)日：1989-06-07

申请号：EP86104999.7

申请日：1986-04-11

申请人： International Business Machines Corporation

发明人： Ellis, Joseph John, Jr.

IPC分类号： G09G3/28

CPC分类号： G09G3/28 ,  G09G2310/0286 ,  G09G2360/121

摘要： A display system is disclosed comprising a processor, a plasma panel subassembly including generally orthogonally related arrays of conductors an drive circuits for the same, and a read-write memory for storing the image data provided by the processor and delivering drive information to the panel subassembly. Control logic provides arbitration for time sharing the operation of the memory between communication with the processor and with the panel subassembly, storage or modified data tags means associated with the memory operation, and means under the control of the modified data tag means to control update erase and write operations of the panel subassembly on and as-needed individual pel line basis.

公开(公告)号：EP3176773B1

公开(公告)日：2018-10-17

申请号：EP16201677.8

申请日：2016-12-01

申请人： LG Display Co., Ltd.

发明人： KIM, Daeku ,  KWANG, Heekwang ,  LEE, Chooghoon ,  JUNG, Yoonjoon

IPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G3/3275

CPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/0439 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0216 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08

摘要： An organic light emitting diode display is discussed. The organic light emitting diode display includes a display area, in which first scan lines, second scan lines, and emission lines are disposed to intersect data lines, and pixels are disposed in a matrix, a data driver supplying a data voltage to the data lines, and a shift register supplying a first scan signal to the first scan lines, supplying a second scan signal to the second scan lines, and supplying an emission control signal to the emission lines. The shift register includes first scan signal stages sequentially supplying the first scan signal to pixels arranged on two adjacent horizontal lines, second scan signal stages sequentially supplying the second scan signal to the pixels, and an emission control signal stage simultaneously supplying the emission control signal to the pixels.

公开(公告)号：EP3370235A2

公开(公告)日：2018-09-05

申请号：EP18159659.4

申请日：2018-03-02

申请人： AU Optronics Corporation

发明人： WANG, Chun-Min ,  WEI, Lin-Chieh

IPC分类号： G11C19/28 ,  G09G3/36 ,  G09G3/3266

CPC分类号： G09G3/3688 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0286 ,  G11C19/28

摘要： A display panel (100) includes multiple gate lines (G1-G10) and a gate driver (120). The gate driver includes multiple shift registers (SR1-SR10, 200). Each of the shift registers includes a pull-up circuit (210), a driving circuit (220), and a pull-down circuit (230). The pull-up circuit charges a first node (NQ) in the shift register. The driving circuit is coupled to the first node, and outputs, according to a voltage signal of the first node, a driving pulse signal (G[n]) to a corresponding gate line. The pull-down circuit is coupled to the driving circuit, and discharges one of the gate lines according to the voltage signal of the first node. The shift register includes a first shift register (SRI) provided on a first side and a second shift register (SR2) provided on a second side. The pull-down circuit in the first shift register discharges a gate line corresponding to the second shift register according to the voltage signal of the first node.

公开(公告)号：EP3367376A1

公开(公告)日：2018-08-29

申请号：EP16856809.5

申请日：2016-09-28

申请人： BOE Technology Group Co., Ltd.

发明人： CHOI, Hyun Sic ,  HAN, Seung Woo

IPC分类号： G09G3/36

CPC分类号： G11C19/186 ,  G09G3/2092 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/028 ,  G09G2330/06 ,  G11C19/188 ,  G11C19/287

摘要： A shift register unit and a method for control same, a gate drive device comprising the shift register unit, and a display device comprising the gate drive device. The shift register unit comprises: an input module (21), a pull-up module (22), a first pull-down control signal generation module (23), controlling, in the period in which a first signal is high level, the potential of a first pull-down control node according to the potential of a drive input signal and a pull-up control node; a second pull-down control signal generation module (24), controlling, in the period in which a second signal is high level, the potential of a second pull-down control node according to the potential of the drive input signal and the pull-up control node, the first signal and the second signal alternatively turning to high level; a pull-down module (25), pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node. This is able to improve the stability of the gate drive circuit, thereby performing displaying reliably.

公开(公告)号：EP3361472A1

公开(公告)日：2018-08-15

申请号：EP16852863.6

申请日：2016-09-30

申请人： BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

发明人： WANG, Zheng

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C7/1036 ,  G11C7/20 ,  G11C19/28 ,  G11C19/30 ,  G11C29/022 ,  G11C29/86

摘要： A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module (200) connected between an input terminal (INPUT) and a pull-up node (PU), and configured to charge the pull-up node (PU); an output module (205) connected between the pull-up node (PU), a first clock signal terminal (CK) and an output terminal (OUTPUT), and configured to output to the output terminal (OUTPUT) a first clock signal received at the first clock signal terminal (CK); a pull-up node reset module (215) connected between a reset terminal (RESET-IN), a pull-down node (PD) and the pull-up node (PU), and configured to reset the pull-up node (PU); and an output reset module (220) connected between a second clock signal terminal (CKB), the pull-down node (PD) and the output terminal (OUTPUT), and configured to reset the output terminal (OUTPUT). The shift register unit, a gate line driving device and a driving method can downsize an overall structure of the GOA, reduce power consumption, decrease signal delay, improve signal waveform, and also enhance reliability of the GOA circuit in entirety.

公开(公告)号：EP3353771A1

公开(公告)日：2018-08-01

申请号：EP16775055.3

申请日：2016-09-20

申请人： Apple Inc.

发明人： VAHID FAR, Mohammad B. ,  BAE, Hopil ,  BAROUGHI, Mahid Farrokh ,  WANG, Xiaofeng

IPC分类号： G09G3/3266 ,  G09G3/3225 ,  G09G3/20 ,  G09G3/00

CPC分类号： G09G3/2003 ,  G09G3/006 ,  G09G3/2022 ,  G09G3/3208 ,  G09G3/3225 ,  G09G3/3266 ,  G09G2300/0804 ,  G09G2310/0286 ,  G09G2320/0693 ,  G09G2330/026 ,  G09G2330/08 ,  G11C19/287

摘要： An electronic display includes an active area including multiple pixels. The electronic display also includes a first row driver set including a first column of row drivers and a second column of row drivers. A first active row driver in the first column of row drivers drives a first portion of the multiple pixels, and a first spare row driver in the second column of row drivers is in an inactive state. The electronic display also includes a second row driver set including a third column of row drivers and a fourth column of row drivers. A third active row driver in the third column of row drivers drives a second portion of the multiple pixels, and a second spare row driver in the fourth column of row drivers is inactive.

公开(公告)号：EP3249638A4

公开(公告)日：2018-07-25

申请号：EP15878458

申请日：2015-04-15

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： WU ZHONGYUAN

IPC分类号： G09G3/20 ,  G11C19/28

CPC分类号： G09G5/003 ,  G09G3/20 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

摘要： Embodiments of the present invention disclose a GOA unit and a driving method, a GOA circuit and a display device, which relates to the field of manufacture of display, for reducing the area of the gate driving circuit and reducing the power consumption of the gate driving circuit. The GOA unit comprises an input module, a reset module, a control module, a first output control module, a second output control module and a feedback module. The embodiments of the present invention are used for manufacture of display.

公开(公告)号：EP2827335B1

公开(公告)日：2018-07-18

申请号：EP13760746.1

申请日：2013-03-05

申请人： Sharp Kabushiki Kaisha

发明人： HORIUCHI, Satoshi ,  TANAKA, Shinya ,  TAGAWA, Akira ,  IWASE, Yasuaki ,  MIZUNAGA, Takayuki ,  IWAMOTO, Akihisa

IPC分类号： G11C19/28 ,  G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0286 ,  G11C19/28 ,  G11C27/04

摘要： A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.