公开(公告)号：EP4202996A3

公开(公告)日：2023-09-20

申请号：EP22205708.5

申请日：2022-11-07

申请人： Intel Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand ,  GLASS, Glenn ,  SHAH, Rushabh ,  GHOSE, Susmita

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/775

摘要： An integrated circuit structure includes a first non-planar semiconductor device (101) and a second non-planar semiconductor device (151). The first non-planar semiconductor device includes a first body (118a, 118b, 118c), a first gate structure (132, 120) at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body (168a, 168b, 168c), a second gate structure (170, 182) at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height (hL) of the first body is at least 5% different from a second height (hH) of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：EP3155656A1

公开(公告)日：2017-04-19

申请号：EP14894732.8

申请日：2014-06-13

申请人： Intel Corporation

发明人： JUN, Kimin ,  RACHMADY, Willy ,  GLASS, Glenn ,  MURTHY, Anand

IPC分类号： H01L21/56

CPC分类号： H01L29/161 ,  H01L21/02532 ,  H01L21/2007 ,  H01L21/56 ,  H01L21/76251 ,  H01L23/298 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/50

摘要： Techniques are disclosed for wafer bonding with an encapsulation layer. A first semiconductor substrate is provided. An encapsulation layer is then formed on top of the first semiconductor substrate. The encapsulation layer is formed of an encapsulation material that creates a stable oxide when exposed to an oxidizing agent. A first bonding layer is formed on top of the encapsulation layer. Next, a second semiconductor substrate is provided. A second bonding layer is formed on top of the second bonding layer. Thereafter, the first semiconductor substrate is bonded to the second semiconductor substrate by attaching the first bonding layer to the second bonding layer.

摘要翻译： 公开了用于封装层的晶圆键合的技术。 提供第一半导体衬底。 然后在第一半导体衬底的顶部上形成封装层。 封装层由暴露于氧化剂时产生稳定氧化物的封装材料形成。 第一接合层形成在封装层的顶部上。 接下来，提供第二半导体衬底。 第二结合层形成在第二结合层的顶部上。 之后，通过将第一结合层附着到第二结合层来将第一半导体衬底结合到第二半导体衬底。

公开(公告)号：EP1428263B1

公开(公告)日：2011-10-05

申请号：EP03764362.4

申请日：2003-07-03

申请人： Intel Corporation

发明人： MURTHY, Anand ,  DOYLE, Brian ,  KAVALIEROS, Jack ,  CHAU, Robert

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

公开(公告)号：EP1634336A1

公开(公告)日：2006-03-15

申请号：EP03800017.0

申请日：2003-12-18

申请人： INTEL CORPORATION

发明人： BOYANOV, Boyan ,  DOYLE, Brian ,  KAVALIEROS, Jack ,  MURTHY, Anand ,  CHAU, Robert

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

摘要： There is disclosed an apparatus including a straining substrate (150), a device over the substrate including a channel (594, 494), wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

摘要翻译： 一种装置，包括：具有基板表面的基板（150） 其特征在于包括装置主体（154）的衬底表面上方的装置（152），所述装置主体（154）包括形成在主体（154）的侧壁表面（136,236）中的通道（494,594） 第一结区（203）和第二结区（203）; 其中所述主体（154）还包括：栅电极（130,230），其中所述第一接合区域（203）和所述第二接合区域（303）邻近所述栅电极设置; 并且其中所述衬底具有不同于所述主体（154）的晶格间距的晶格间距，其中所述主体（154）适于在所述通道（494,594）中具有大致垂直于所述主体（154）的表面的电流 衬底（150）。

公开(公告)号：EP1602126A1

公开(公告)日：2005-12-07

申请号：EP03797023.3

申请日：2003-12-15

申请人： INTEL CORPORATION

发明人： DOYLE, Brian ,  MURTHY, Anand ,  CHAU, Robert

IPC分类号： H01L21/20

CPC分类号： H01L29/66795 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L29/125 ,  H01S5/341

摘要： A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left-between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

公开(公告)号：EP4203071A1

公开(公告)日：2023-06-28

申请号：EP22201885.5

申请日：2022-10-17

申请人： INTEL Corporation

发明人： BOMBERGER, Cory C. ,  JAMBUNATHAN, Karthik ,  MURTHY, Anand ,  NAM, Ju ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08

摘要： In one embodiment, an integrated circuit includes a substrate, a buffer layer, a source region, a drain region, a channel region, and a gate structure. The substrate includes silicon. The buffer layer is above the substrate and includes a semiconductor material having defects near an interface with the substrate. The buffer layer also includes ions implanted among the defects. The source region and drain region are above the buffer layer, and the channel region is above the buffer layer and between the source and drain regions. The gate structure above the channel region.

公开(公告)号：EP4203023A1

公开(公告)日：2023-06-28

申请号：EP22214306.7

申请日：2022-12-16

申请人： INTEL Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/538

摘要： An apparatus includes a first layer comprising silicon, and a conductive feature extending within the silicon of the first layer. The conductive feature includes (i) conductive material extending throughout the length of the conductive feature, (ii) a barrier layer between the conductive material and the silicon of the first layer, and (iii) a second layer including dielectric material between the barrier layer and the silicon of the first layer. In an example, one or more discontinuous monolayers of metal are between sections of the dielectric material and the silicon of the first layer. The conductive feature is formed in a recess extending within the silicon of the first layer. In an example, the recess is formed using a metal assisted etch process using the metal as a catalyst, and one or more discontinuous monolayers of the metal are remnants of the metal used in the metal assisted etch process.

公开(公告)号：EP4202996A2

公开(公告)日：2023-06-28

申请号：EP22205708.5

申请日：2022-11-07

申请人： Intel Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand ,  GLASS, Glenn ,  SHAH, Rushabh ,  GHOSE, Susmita

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/775

摘要： An integrated circuit structure includes a first non-planar semiconductor device (101) and a second non-planar semiconductor device (151). The first non-planar semiconductor device includes a first body (118a, 118b, 118c), a first gate structure (132, 120) at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body (168a, 168b, 168c), a second gate structure (170, 182) at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height (hL) of the first body is at least 5% different from a second height (hH) of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：EP4185094A1

公开(公告)日：2023-05-24

申请号：EP22200347.7

申请日：2022-10-07

申请人： INTEL Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand

IPC分类号： H10N97/00 ,  H01L23/522

摘要： Multi-plate MIM capacitors include a staircase structure, with steps including a high-k capacitor dielectric and one or more electrode plates. Contacts pass through insulator fill material and land on the electrode plate of a respective step. A recess passes through the staircase structure. In some examples, the recess is filled with insulator material, and steps of the staircase structure have a bilayer structure (e.g., lower layer of capacitor dielectric and upper layer of capacitor electrode plate). In other examples, the recess is filled with conductive material. In such cases, steps of the staircase structure have a multilayer structure that includes an upper portion and a lower portion. The lower portion includes insulator material and the upper portion includes a layer of capacitor dielectric between first and second capacitor electrode plates, with the second capacitor electrode plates being continuous with, or otherwise in contact with, the conductive material in the recess.

公开(公告)号：EP4156293A1

公开(公告)日：2023-03-29

申请号：EP22189549.3

申请日：2022-08-09

申请人： Intel Corporation

发明人： GHANI, Tahir ,  MURTHY, Anand ,  PATEL, Pratik ,  KEECH, Ryan ,  HASAN, Mohammad ,  RAFIQUE, Subrina ,  GANGULY, Koustav

IPC分类号： H01L29/775 ,  H01L29/08 ,  H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/306 ,  H01L21/20 ,  B82Y10/00

摘要： Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials. In particular a nanosheet FET (1000) is disclosed, with nanosheets (108), gate (1001) and epitaxially grown source/drain materials (106, 107). The width of the source/drain regions is larger than the width of the nanosheets, but not more than one-third.