公开(公告)号：EP4195289A1

公开(公告)日：2023-06-14

申请号：EP22204877.9

申请日：2022-11-01

申请人： INTEL Corporation

发明人： SEN GUPTA, Arnab ,  DEWEY, Gilbert ,  CHOUKSEY, Siddharth ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack ,  METZ, Mathew ,  CLENDENNING, Scott ,  RETASKET, Jason ,  JOHNSON, Edward

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L29/78

摘要： Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：EP4177938A1

公开(公告)日：2023-05-10

申请号：EP22199064.1

申请日：2022-09-30

申请人： INTEL Corporation

发明人： HUANG, Cheng-Ying ,  ALAAN, Urusa ,  GHOSE, Susmita ,  NAHM, Rambert ,  BRIGGS, Natalie ,  THOMAS, Nicole ,  RACHMADY, Willy ,  RADOSAVLJEVIC, Marko ,  KAVALIEROS, Jack

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/775

摘要： Techniques are provided herein to form gate-all-around (GAA) semiconductor devices (100), such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons (104, 108) extending in the same (e.g., horizontal) direction where one device (101) is located vertically above the other device (103). An internal spacer structure (118) extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features (120) between the two devices. A gate structure (114) that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

公开(公告)号：EP4016625A1

公开(公告)日：2022-06-22

申请号：EP21194830.2

申请日：2021-09-03

申请人： INTEL Corporation

发明人： Shivaraman, Shriram ,  AVCI, Uygar E. ,  Chang, Sou-Chi ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack

IPC分类号： H01L27/11514

摘要： Plate line architectures for 3D-Ferroelectric Random Access Memory (3D-FRAM) are described. In an example, a memory device includes a plurality of bitlines (108) along a first direction and a plurality of wordlines (110) along a second direction orthogonal to the first direction. An access transistor (106) is at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines (PL1, ..., PL4) and insulating material (118) are fabricated over the access transistor. Two or more ferroelectric capacitors (102) are over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor.

公开(公告)号：EP3832735A2

公开(公告)日：2021-06-09

申请号：EP20198182.6

申请日：2020-09-24

申请人： INTEL Corporation

发明人： SUNG, Seung Hoon ,  PENUMATCHA, Ashish Verma ,  CHANG, Sou-Chi ,  MERRILL, Devin ,  TUNG, I-Cheng ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack ,  YOUNG, Ian ,  METZ, Matthew ,  AVCI, Uygar ,  LIN, Chia-Ching ,  LOH, Owen ,  SHIVARAMAN, Shriram ,  MATTSON, Eric

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51

摘要： A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：EP3624200A1

公开(公告)日：2020-03-18

申请号：EP19183091.8

申请日：2019-06-28

申请人： INTEL Corporation

发明人： GLASS, Glenn ,  MURTHY, Anand ,  BOMBERGER, Cory ,  GHANI, Tahir ,  KAVALIEROS, Jack ,  CHOUKSEY, Siddarth ,  SUNG, Seung Hoon ,  GUHA, Biswajeet ,  AGRAWAL, Ashish

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/78

摘要： A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：EP1573803A2

公开(公告)日：2005-09-14

申请号：EP03814832.6

申请日：2003-12-15

申请人： INTEL CORPORATION

发明人： DOCZY, Mark ,  KEATING, Steven ,  KAVALIEROS, Jack ,  DOYLE, Brian ,  BARNS, Chris ,  BARNAK, John ,  MCSWINEY, Michael ,  BRASK, Justin

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

公开(公告)号：EP3709343A1

公开(公告)日：2020-09-16

申请号：EP20152791.8

申请日：2020-01-21

申请人： Intel Corporation

发明人： DEWEY, Gilbert ,  KAVALIEROS, Jack ,  RACHMADY, Willy ,  HUANG, Cheng-Ying ,  METZ, Matthew ,  JUN, Kimin ,  MORROW, Patrick ,  LILAK, Aaron ,  MANNEBACH, Ehren ,  PHAN, Anh

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06

摘要： Disclosed herein are stacked transistors having device strata (130-1, 130-2) with different channel widths (136-1, 136-2), as well as related methods and devices. In some embodiments, an integrated circuit structure (100) may include stacked strata of transistors, wherein different channel materials (106-1, 106-2) of different strata have different widths.

公开(公告)号：EP3706167A1

公开(公告)日：2020-09-09

申请号：EP20153095.3

申请日：2020-01-22

申请人： INTEL Corporation

发明人： LIN, Chia-Ching ,  CHANG, Sou-Chi ,  PENUMATCHA, Ashish Verma ,  HARATIPOUR, Nazila ,  SUNG, Seung Hoon ,  LOH, Owen Y. ,  KAVALIEROS, Jack ,  AVCI, Uygar E. ,  YOUNG, Ian A.

IPC分类号： H01L27/11507 ,  H01L49/02 ,  H01G4/005 ,  H01G4/33

摘要： Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

公开(公告)号：EP1428263B1

公开(公告)日：2011-10-05

申请号：EP03764362.4

申请日：2003-07-03

申请人： Intel Corporation

发明人： MURTHY, Anand ,  DOYLE, Brian ,  KAVALIEROS, Jack ,  CHAU, Robert

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

公开(公告)号：EP2359394A2

公开(公告)日：2011-08-24

申请号：EP09837819.3

申请日：2009-12-07

申请人： Intel Corporation

发明人： MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  METZ, Matthew V. ,  CHAU, Robert S. ,  KAVALIEROS, Jack

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.