公开(公告)号：EP3624200A1

公开(公告)日：2020-03-18

申请号：EP19183091.8

申请日：2019-06-28

申请人： INTEL Corporation

发明人： GLASS, Glenn ,  MURTHY, Anand ,  BOMBERGER, Cory ,  GHANI, Tahir ,  KAVALIEROS, Jack ,  CHOUKSEY, Siddarth ,  SUNG, Seung Hoon ,  GUHA, Biswajeet ,  AGRAWAL, Ashish

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/78

摘要： A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：EP4203059A1

公开(公告)日：2023-06-28

申请号：EP22203503.2

申请日：2022-10-25

申请人： INTEL Corporation

发明人： SHAH, Rushabh ,  GLASS, Glenn ,  HASAN, Mohammad ,  MURTHY, Anand ,  BOMBERGER, Cory

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00

摘要： Cap layers (144) are formed on silicon germanium (SiGe) source/drain regions (140) of field-effect transistors, in particular FinFETs and GAA-FETs, to provide etch resistance to processing steps that can occur in a semiconductor manufacturing process between formation of the SiGe source/drain regions and metal contact (152) formation. The cap layers (144) comprise boron and are thin (e.g., 2 nm or less) to provide for a low metal contact resistance. The atomic concentration of boron in the cap layer is in a range of about 0.2-20%, and the cap layer preferably further comprises Si and Ge. In addition to providing etch resistance, the cap layer provides for a thermally stable contact resistance as the cap layer can prevent or limit the creation of voids in the SiGe layer by preventing or limiting the diffusion of germanium from the SiGe layer into the metal (148, 152) in subsequent annealing and other high-temperature processing steps.As metal-silicon-germanium region (168) is preferably formed between the source/drain region (140) and the metal contact (152).

公开(公告)号：EP4202996A3

公开(公告)日：2023-09-20

申请号：EP22205708.5

申请日：2022-11-07

申请人： Intel Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand ,  GLASS, Glenn ,  SHAH, Rushabh ,  GHOSE, Susmita

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/775

摘要： An integrated circuit structure includes a first non-planar semiconductor device (101) and a second non-planar semiconductor device (151). The first non-planar semiconductor device includes a first body (118a, 118b, 118c), a first gate structure (132, 120) at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body (168a, 168b, 168c), a second gate structure (170, 182) at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height (hL) of the first body is at least 5% different from a second height (hH) of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：EP3155656A1

公开(公告)日：2017-04-19

申请号：EP14894732.8

申请日：2014-06-13

申请人： Intel Corporation

发明人： JUN, Kimin ,  RACHMADY, Willy ,  GLASS, Glenn ,  MURTHY, Anand

IPC分类号： H01L21/56

CPC分类号： H01L29/161 ,  H01L21/02532 ,  H01L21/2007 ,  H01L21/56 ,  H01L21/76251 ,  H01L23/298 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/50

摘要： Techniques are disclosed for wafer bonding with an encapsulation layer. A first semiconductor substrate is provided. An encapsulation layer is then formed on top of the first semiconductor substrate. The encapsulation layer is formed of an encapsulation material that creates a stable oxide when exposed to an oxidizing agent. A first bonding layer is formed on top of the encapsulation layer. Next, a second semiconductor substrate is provided. A second bonding layer is formed on top of the second bonding layer. Thereafter, the first semiconductor substrate is bonded to the second semiconductor substrate by attaching the first bonding layer to the second bonding layer.

摘要翻译： 公开了用于封装层的晶圆键合的技术。 提供第一半导体衬底。 然后在第一半导体衬底的顶部上形成封装层。 封装层由暴露于氧化剂时产生稳定氧化物的封装材料形成。 第一接合层形成在封装层的顶部上。 接下来，提供第二半导体衬底。 第二结合层形成在第二结合层的顶部上。 之后，通过将第一结合层附着到第二结合层来将第一半导体衬底结合到第二半导体衬底。

公开(公告)号：EP4449500A1

公开(公告)日：2024-10-23

申请号：EP22908555.0

申请日：2022-11-03

申请人： INTEL Corporation

发明人： MURTHY, Anand ,  MAJHI, Prashant ,  GLASS, Glenn

IPC分类号： H01L27/092 ,  H01L29/04 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

公开(公告)号：EP3394898A1

公开(公告)日：2018-10-31

申请号：EP15911549.2

申请日：2015-12-24

申请人： Intel Corporation

发明人： JAMBUNATHAN, Karthik ,  GLASS, Glenn ,  MURTHY, Anand ,  KANG, Jun, Sung ,  KIM, Seiyon

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78

摘要： Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.

公开(公告)号：EP3394896A1

公开(公告)日：2018-10-31

申请号：EP15911509.6

申请日：2015-12-24

申请人： Intel Corporation

发明人： GLASS, Glenn ,  JAMBUNATHAN, Karthik ,  MURTHY, Anand ,  MOHAPATRA, Chandra ,  KIM, Seiyon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：EP4297075A1

公开(公告)日：2023-12-27

申请号：EP23170147.5

申请日：2023-04-26

申请人： INTEL Corporation

发明人： KAVALIEROS, Jack ,  RADOSAVLJEVIC, Marko ,  GLASS, Glenn ,  BUDREVICH, Aaron ,  AGRAWAL, Ashish ,  SUNG, Seung Hoon ,  BOWONDER, Anupama ,  PAUL, Rajat ,  GUHA, Biswajeet ,  NAHM, Rambert ,  MERRILL, Devin ,  ONI, Adedapo ,  HSU, William ,  GHOSE, Susmita ,  SUBRAMANIAN, Shruti ,  BRIGGS, Natalie ,  RAMAMURTHY, Rahul ,  TSENG, Hsin-Ying

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：EP4202996A2

公开(公告)日：2023-06-28

申请号：EP22205708.5

申请日：2022-11-07

申请人： Intel Corporation

发明人： MAJHI, Prashant ,  MURTHY, Anand ,  GLASS, Glenn ,  SHAH, Rushabh ,  GHOSE, Susmita

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/775

摘要： An integrated circuit structure includes a first non-planar semiconductor device (101) and a second non-planar semiconductor device (151). The first non-planar semiconductor device includes a first body (118a, 118b, 118c), a first gate structure (132, 120) at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body (168a, 168b, 168c), a second gate structure (170, 182) at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height (hL) of the first body is at least 5% different from a second height (hH) of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：EP4152363A1

公开(公告)日：2023-03-22

申请号：EP22198320.8

申请日：2013-09-26

申请人： INTEL Corporation

发明人： JACKSON, Michael ,  MURTHY, Anand ,  GLASS, Glenn ,  MORARKA, Saurabh ,  MOHAPATRA, Chandra

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/32 ,  H01L29/165

摘要： A strained-channel FET transistor comprising a single-crystal semiconductor substrate of a material having a first lattice constant; a channel region of the single-crystal semiconductor substrate; a gate dielectric disposed between a gate electrode and the channel region of the single-crystal semiconductor substrate; a source region having a source nucleation layer having a second lattice constant different from the first lattice constant within a first opening in the single-crystal semiconductor substrate on a first side of the channel region; and a drain region having a drain nucleation layer having the second lattice constant within a second opening of the single-crystal semiconductor substrate on a second side of the channel region opposite the first side of the channel region, wherein each of the source and drain nucleation layers is configured to cause crystalline dislocations in the source and drain regions.