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24 条记录 (耗时 0.01 秒)

    Semiconductor device with vertical transistor and buried word line
    13.
    发明公开
    Semiconductor device with vertical transistor and buried word line 有权
    Halbleiterbauteil mit vertikalem晶体管和Vergrabener Wortleitung

    公开(公告)号：EP0948053A2

    公开(公告)日：1999-10-06

    申请号：EP99102355.7

    申请日：1999-02-06

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Rupp, Thomas ,  Alsmeier, Johann

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.

    摘要翻译： 字线埋在垂直半导体器件旁边。 字线被嵌入与垂直半导体器件相邻，使得字线的形貌基本上是平面的。 掩埋字线的平面特征允许在字线和垂直晶体管上执行进一步处理。 在另一个实施例中，垂直半导体器件是具有垂直取向栅极的晶体管。 字线被埋在垂直取向的栅极旁边，使得字线的形状基本上是平面的。

    Shallow trench isolation for DRAM trench capacitor
    14.
    发明公开
    Shallow trench isolation for DRAM trench capacitor 失效
    Flakgraben隔离DRAM缩放器

    公开(公告)号：EP0908948A2

    公开(公告)日：1999-04-14

    申请号：EP98110953.1

    申请日：1998-06-16

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate to reduce oxidation stress.

    摘要翻译： 一种随机存取存储单元，其具有形成在衬底表面下方的沟槽电容器。 提供浅沟槽隔离以将存储器单元与存储器阵列的其它存储器单元隔离。 浅沟槽隔离包括在衬底上方升高以降低氧化应力的顶表面。

    CMOS Integrated circuits with reduced substrate defects
    15.
    发明公开
    CMOS Integrated circuits with reduced substrate defects 失效
    Integrierte CMOS-Schaltungen mit reduzierten Substratdefekten

    公开(公告)号：EP0889517A1

    公开(公告)日：1999-01-07

    申请号：EP98109831.2

    申请日：1998-05-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann ,  Wangemann, Klaus

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/763

    CPC分类号： H01L21/763 ,  H01L21/823878 ,  H01L27/0921

    摘要： A complementary metal oxide (CMOS) integrated circuit configured for reducing the formation of silicon defects in its silicon substrate during manufacture. The silicon defects are formed from silicon interstitials present in the silicon substrate. The CMOS integrated circuit includes a deep implantation region formed within the silicon substrate. There is further included at least one vertical trench formed in the silicon substrate. The trench is formed such that at least a portion of the trench penetrates into the deep implantation region of the silicon substrate to present vertical surfaces within the deep implantation region, thereby allowing the silicon interstitials to recombine at the vertical surfaces.

    摘要翻译： 互补金属氧化物（CMOS）集成电路，其被配置为在制造期间减少其硅衬底中的硅缺陷的形成。 硅缺陷由存在于硅衬底中的硅间隙形成。 CMOS集成电路包括形成在硅衬底内的深注入区域。 还包括在硅衬底中形成的至少一个垂直沟槽。 沟槽形成为使得沟槽的至少一部分穿透到硅衬底的深注入区域中以在深注入区域内呈现垂直表面，从而允许硅间隙在垂直表面处复合。

    Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS
    17.
    发明公开
    Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS 失效
    一种用于通过一个信道沟减少begrabenem具有有限在p-MOSFET的异常窄沟道效应的方法

    公开(公告)号：EP0720218A2

    公开(公告)日：1996-07-03

    申请号：EP95119309.3

    申请日：1995-12-07

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Alsmeier, Johann ,  Mandelman, Jack A.

    IPC分类号： H01L21/76 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L27/10873 ,  H01L21/823412 ,  H01L29/7838

    摘要： Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850°C gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850°C gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850°C gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850°C gate oxidation step may follow the RTO gate oxidation step.

    Deep trench DRAM process on SOI for low leakage DRAM cell
    19.
    发明公开
    Deep trench DRAM process on SOI for low leakage DRAM cell 失效
    Tiefgraber-DRAM-Prozess auf SOIfürDRAM-Zelle niedrigen Leckstromes

    公开(公告)号：EP0703625A3

    公开(公告)日：1999-03-03

    申请号：EP95114657.0

    申请日：1995-09-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Alsmeier, Johann ,  Stengl, Reinhard Johannes

    IPC分类号： H01L27/108 ,  H01L21/82

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/1203

    摘要： A deep trench DRAM cell is formed on a silicon on isolator (SOI) substrate, with a buried strap formed by outdiffusion of dopant in associated trench node material, for providing an electrical connection between the trench node and the active area of a MOS transfer gate formed in the substrate adjacent the trench in an uppermost portion of the substrate.

    摘要翻译： 在隔离器（SOI）衬底上的硅上形成深沟槽DRAM单元，其中通过相关沟槽节点材料中的掺杂剂的扩散扩散形成的掩埋带，用于在沟槽节点和MOS传输栅极的有源区之间提供电连接 在衬底中邻近衬底的最上部形成的衬底。