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18 条记录 (耗时 0.015 秒)

    Method of forming buried strap for trench capacitor
    11.
    发明公开
    Method of forming buried strap for trench capacitor 审中-公开
    Verfahren zur Herstellung eines vergrabenen Verbindungsstreifensfüreinen Grabenkondensator

    公开(公告)号：EP0949674A2

    公开(公告)日：1999-10-13

    申请号：EP99302567.5

    申请日：1999-03-31

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Gruening, Ulrike ,  Jaiprakash, Venkatachalam C. ,  Bronner, Gary ,  Radens, Carl ,  Beintner, Jochen

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： The invention relates to reducing variations in thickness and height of the buried strap of a trench capacitor. Reduced variations in thickness and height is achieved by defining the top of the buried strap by recessing the poly in the trench to the top of the buried strap. The collar is then recessed to below the top surface to define the bottom of the buried strap. A poly layer is deposited to line the sidewalls of the trench top surface of the poly trench fill, and recessed region above the collar. A etch is then used to remove the excess poly layer from the sidewalls and top surface of the poly trench fill, leaving the recessed region above the collar filled to form the buried strap. The etch removes the poly in the vertical and horizontal direction at about the same rate.

    摘要翻译： 本发明涉及减小沟槽电容器的掩埋带的厚度和高度的变化。 通过将沟槽中的多孔凹入掩埋带的顶部来限定掩埋带的顶部来实现厚度和高度的减小。 然后将套环凹入到顶部表面下方以限定掩埋带的底部。 沉积聚层以使多沟槽填充物的沟槽顶表面的侧壁和套环上方的凹陷区域对齐。 然后使用蚀刻从多沟槽填充物的侧壁和顶表面去除多余的多晶硅层，从而使填充的套环上方的凹陷区域形成掩埋带。 该蚀刻以大致相同的速率在垂直和水平方向上去除多晶。

    Buffer layer for improving control of layer thickness
    12.
    发明公开
    Buffer layer for improving control of layer thickness 有权
    缓冲层用于改善层厚控制

    公开(公告)号：EP0908938A2

    公开(公告)日：1999-04-14

    申请号：EP98307803.1

    申请日：1998-09-25

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Gruening, Ulrike ,  Beintner, Jochen ,  Radens, Carl

    IPC分类号： H01L21/31 ,  H01L21/314 ,  H01L21/033 ,  H01L21/762

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/763 ,  H01L27/10867 ,  Y10S438/97

    摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

    摘要翻译： 设置在半导体衬底102上的衬垫层和设置在衬垫层内的缓冲层108，使得衬垫层被分成缓冲层下方的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平面性和厚度的层的方法包括以下步骤：提供其上形成有热垫106的衬底;在热垫上形成介电层106;在介电层上形成缓冲层108，其中 缓冲层由与介电层不同的材料制成并且在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

    DRAM trench capacitor cell
    14.
    发明公开
    DRAM trench capacitor cell 审中-公开
    DRAM沟槽电容器单元

    公开(公告)号：EP1017095A2

    公开(公告)日：2000-07-05

    申请号：EP99310310.0

    申请日：1999-12-21

    申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

    发明人： Radens, Carl ,  Gruening, Ulrike ,  DeBrosse, John ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876

    摘要： A memory cell formed in a semiconductor body includes a vertical trench with a polysilicon fill as a storage capacitor and a field effect transistor having a source formed in the sidewall of the trench, a drain formed in the semiconductor body and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer at the top of the polysilicon fill portion that serves as the storage node and the polysilicon fill portion that serves as the gate conductor.

    摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物的垂直沟槽和具有形成在沟槽的侧壁中的源极的场效应晶体管，形成在半导体本体中并且具有与 并且具有包括垂直部分和水平部分的沟道区域以及位于沟道上部的多晶硅栅极。 用于制造的工艺在用作存储节点的多晶硅填充部分的顶部和用作栅极导体的多晶硅填充部分处提供绝缘氧化物层。

    Improved process for buried-strap self-aligned to deep storage trench
    17.
    发明公开
    Improved process for buried-strap self-aligned to deep storage trench 审中-公开
    Verbeetes Verfahrenfürein zu einem tiefen Speichergraben selbstjustiertes，vergrabenes Band

    公开(公告)号：EP1022782A2

    公开(公告)日：2000-07-26

    申请号：EP00100875.4

    申请日：2000-01-18

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Grüning, Ulrike ,  Mandelman, Jack ,  Radens, Carl

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

    摘要翻译： 一种用于形成与深存储沟槽自对准的掩埋带的工艺。 垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。 插塞形成在间隔件之间的区域中。 光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。 对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。 不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。 选择性地蚀刻衬底和通过间隔物去除而暴露的填充深沟槽的部分。 在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中形成隔离区。