公开(公告)号：EP1864224A2

公开(公告)日：2007-12-12

申请号：EP06739000.5

申请日：2006-03-17

申请人： International Business Machines Corporation

发明人： BLUMRICH, Matthias A. ,  GARA, Alan G. ,  SALAPURA, Valentina

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0822 ,  G06F2212/507 ,  Y02D10/13

摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.

公开(公告)号：EP1739561A1

公开(公告)日：2007-01-03

申请号：EP06291069.0

申请日：2006-06-28

申请人： STMicroelectronics SA

发明人： Cousin, Jean-Philippe ,  Berenguer, Jean-José ,  Plessier, Gilles

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0831

摘要： L'invention propose un procédé mettant en cohérence la mémoire cache (22) d'un processeur (2), dans lequel:
-le processeur traite (E1a, E1b) une requête d'écriture de données à une adresse de sa mémoire marquée à l'état partagé;
-ladite adresse est transmise (E3) à d'autres processeurs, les données sont écrites (E2a) dans sa mémoire cache (22) et l'adresse passe à l'état modifié, une mémoire annexe (29) mémorise ladite adresse, lesdites données et un marqueur associé (inv) dans un premier état;
-le processeur reçoit (E4) ladite adresse et un indicateur ;
-si l'indicateur indique que le processeur doit effectuer l'opération et si le marqueur associé est dans le premier état, lesdites données sont maintenues à l'état modifié;
-si l'indicateur n'indique pas que le processeur doit effectuer l'opération et si le processeur reçoit une commande de marquage à l'état invalide, le marqueur passe dans un second état.

摘要翻译： 该方法涉及由处理器处理将数据写入处理器的高速缓冲存储器（22）的地址的请求，并将该地址发送到其他处理器。 前一处理器接收指示前一处理器是否必须对地址进行存储器操作的指示符。 如果与数据相关联的标记处于状态，则存储器中的数据保持在修改状态，否则，前一个处理器将共享存储器中的数据写入请求，并将数据标记为无效状态，当指示符指示 执行内存操作。 还包括以下独立权利要求：（1）数字处理器（2）包括若干处理器的系统。

公开(公告)号：EP0882266A1

公开(公告)日：1998-12-09

申请号：EP97908675.0

申请日：1997-02-19

申请人： Intergraph Corporation

发明人： McKINNEY, Arthur, C. ,  McCARVER, Charles, H., Jr. ,  SAMIEE, Vahid

IPC分类号： G06F12 ,  G06F13 ,  G06F15 ,  H03K19

CPC分类号： G06F12/0813 ,  G06F12/0822 ,  G06F12/0831 ,  G06F13/4022 ,  G06F13/4077 ,  G06F15/173 ,  H03K19/00361 ,  H03K19/018521

摘要： The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors. The present invention comprises a plurality of processor segments (a cluster of one or more CPU's) memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel. The processors, in preferred embodiment, may further include an internal cache and flags associated with the cache to allow multi-processor cache coherency in external write-back cache.

公开(公告)号：EP0735483A1

公开(公告)日：1996-10-02

申请号：EP96301932.8

申请日：1996-03-21

申请人： SUN MICROSYSTEMS INC.

发明人： Ebrahim, Zahir ,  Nishtala, Satyanarayana ,  Van Loo, William C. ,  Normoyle, Kevin ,  Lowenstein, Paul ,  Coffin, Louis F., III

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0822

摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transcation requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.

摘要翻译： 在多处理器计算机系统具有子系统的多个和耦合到系统控制器的主存储器。 有些子系统是数据处理器，每个处理器具有一个高速缓冲存储器respectivement那样存储数据的多个块和一组respectivement主高速缓存标签（ETag时）包括一个ETAG用于通过高速缓冲存储器存储的各数据块的。 每个数据处理器包括在接口用于发送存储器事务请求到系统控制器和用于接收高速缓存事务请求从系统控制器向存储器，相应于由数据处理器中的其它transcation请求。 所述系统控制器包括交易激活逻辑，用于激活各所述存储器事务请求时，它满足预定义激活标准，和用于直到预定义的激活标准被满足阻塞每个所述存储器事务请求。 表示存储器事务请求活动事务状态表存储状态数据thathave被激活，包括用于每个激活的事务地址值。 事务激活逻辑包括用于比较与对于所有激活的存储器事务请求活动事务的状态数据的每个存储器事务请求比较器逻辑，以便检测是否一个特定的存储器事务请求的激活将违反预定义的激活条件。 有某些例外关于用于访问一个数据块没有映射到相同的高速缓存行的待处理，先前激活的回写事务的事务传入事务将被阻塞，直到未决事务没有映射到相同的高速缓存行被完成。

公开(公告)号：EP0474450A3

公开(公告)日：1993-07-21

申请号：EP91308023.0

申请日：1991-09-02

申请人： International Business Machines Corporation

发明人： Herzl, Robert Dov ,  Lauricella, Kenneth Anthony ,  Quinn, Linda Legault ,  Schroter, David Andrew ,  Steel, Allan Rowe ,  Temple III, Joseph Lester

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F9/30032 ,  G06F12/0888

摘要： This disclosure describes an efficient method of moving data from one location in memory to another without caching the data. This includes data transfers from one main storage location to another, transfers between main and expanded storage, and transfers from one expanded storage location to another.

公开(公告)号：EP0481233A3

公开(公告)日：1992-04-29

申请号：EP91115825.1

申请日：1991-09-18

申请人： International Business Machines Corporation

发明人： So, Kimming ,  Wang, Wen-Hann

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0822 ,  G06F12/084

摘要： A system and method is disclosed for a multiprocessor system (MP) having multiple levels of cache storage and shared memory. A multiprocessor system (MP) is disclosed which comprises microprocessors (MPU). The MPUs, which have on-chip L₁ caches, are interfaced with external L₂ caches. D₂ directories are situated parallel to the L₂ caches and shadow the L₁ caches. The D₂ directories maintain data coherence among all the caches and a main memory, while decreasing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference with the on-chip L₁ caches. Reducing the amount of interference permits the MPUs to perform at higher speeds and permits the further coupling of additional MPUs to the multiprocessor system (MP).

公开(公告)号：EP0372201A3

公开(公告)日：1991-09-04

申请号：EP89119148.8

申请日：1989-10-16

申请人： International Business Machines Corporation

发明人： Liu, Lishing

IPC分类号： G06F12/08

CPC分类号： G06F12/0822

摘要： A Fetch-Then-Confirm (FTC) policy is used for the handling of data fetch upon XIEX'S in a tightly coupled multiprocessor environment. The fetch and use of a requested data line upon XIEX is allowed before the SCE receives the confirmation of validity (or invalidity) of the requested line through the clearing procedure. Whenever a line having uncertain validity is used by a CP the results of execution of instructions depending on the validity of the line should not be committed to the cache until a confirmation is received from the SCE. When the confirmation from the SCE indicates that a line L is known to be valid, all results depending on the validity of L can be processed as usual. If, however, the SCE indicates that a previously fetched line L having uncertain validity is in fact invalid, all operations performed based on L 's contents should be aborted and restarted properly when a valid copy of L is received.

公开(公告)号：EP0394642A2

公开(公告)日：1990-10-31

申请号：EP90104153.3

申请日：1990-03-03

申请人： International Business Machines Corporation

发明人： Liu, Lishing

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0862 ,  G06F2212/6024

摘要： A method using CH Loc (change-local) type information is used for data prefetch (D-prefetch) decision making. This information is stored in history tables H, there being one such table for each CP at, for example, the buffer control element (BCE). For each line L, H[L] indicates the information for L in H. Two different types of histories may be kept at H:

(1) XI-invalidates - At each H[L], there is recorded whether L was XI-invalidated without refetching.
(2) CH Loc - At each H[L], there is also recorded local-change history, i.e., whether L was stored into since the last fetch.

It is also possible to keep a global H at the storage control element (SCE). In this case, the SCE maintains a table I recording, for each line L, information I[L] recording whether L involved XI-­invalidates during the last accesses by a CP. Upon a cache miss to L from a processor CP i , the SCE prefetches some of those lines that involved XI-­invalidates (indicated by I) into cache C i , if missing there. The management of table I is simple. When an XI-invalidate on L occurs, e.g., upon a store or an EX fetch, the corresponding entry is set. When L is accessed, e.g., upon D-fetch misses, without XI-invalidate, the entry in I is reset. Another criteria for turning an I entry OFF is when the line is fetched, e.g., on demand or upon prefetch.

摘要翻译： 使用CHLoc（变化本地）类型信息的方法用于数据预取（D-prefetch）决策。 该信息被存储在历史表H中，例如在缓冲器控制元件（BCE）处存在用于每个CP的一个这样的表。 对于每行L，H [L]表示H中L的信息。两种不同类型的历史可以保持在H：（1）XI-无效 - 在每个H [L]处，记录L是否是XI- 无需复审即失效。 （2）CHLoc-在每个H [L]处，还记录本地改变历史，即，自上一次提取以来L是否被存储。 也可以在存储控制元素（SCE）上保留全局H。 在这种情况下，SCE维护一个表I，对于每条线L，记录信息I [L]记录在最后一次CP访问期间涉及的L是否无效。 当处理器CPi对L缓存未命中时，SCE将一些涉及XI无效（由I指示）的行预取到缓存Ci中，如果在那里丢失的话。 表I的管理很简单。 当发生L上的XI无效时，例如在存储或EX提取时，相应的条目被设置。 当L被访问时，例如，在D提取未命中时，没有XI无效，I中的条目被重置。 将I入口关闭的另一个标准是在取出该行时，例如根据需要或在预取时。

公开(公告)号：EP0372201A2

公开(公告)日：1990-06-13

申请号：EP89119148.8

申请日：1989-10-16

申请人： International Business Machines Corporation

发明人： Liu, Lishing

IPC分类号： G06F12/08

CPC分类号： G06F12/0822

摘要： A Fetch-Then-Confirm (FTC) policy is used for the handling of data fetch upon XIEX'S in a tightly coupled multiprocessor environment. The fetch and use of a requested data line upon XIEX is allowed before the SCE receives the confirmation of validity (or invalidity) of the requested line through the clearing procedure. Whenever a line having uncertain validity is used by a CP the results of execution of instructions depending on the validity of the line should not be committed to the cache until a confirmation is received from the SCE. When the confirmation from the SCE indicates that a line L is known to be valid, all results depending on the validity of L can be processed as usual. If, however, the SCE indicates that a previously fetched line L having uncertain validity is in fact invalid, all operations performed based on L 's contents should be aborted and restarted properly when a valid copy of L is received.

摘要翻译： Fetch-Then-Confirm（FTC）策略用于在紧密耦合的多处理器环境中处理XIEX'S上的数据提取。 在SCE通过清算程序收到要求行的有效性（或无效）确认之前，可以在XIEX上提取和使用所请求的数据行。 每当CP使用具有不确定有效性的行时，根据线的有效性执行指令的结果不应该被提交到高速缓存，直到从SCE接收到确认。 当来自SCE的确认表明已知行L是有效的时，根据L的有效性的所有结果可以照常进行处理。 然而，如果SCE指示具有不确定有效性的先前获取的行L实际上是无效的，则当接收到L的有效副本时，基于L的内容执行的所有操作应当被中止并正确重新启动。

公开(公告)号：EP0074390A4

公开(公告)日：1986-06-11

申请号：EP82901226

申请日：1982-03-08

申请人： BURROUGHS CORP

发明人： KRONIES REINHARD KURT

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F13/20 ,  G06F15/173 ,  G06F13/00 ,  G06F7/10 ,  G06F7/20 ,  G06F13/06

CPC分类号： G06F12/0822