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    INDIUM-ENHANCED BIPOLAR TRANSISTOR
    11.
    发明公开
    INDIUM-ENHANCED BIPOLAR TRANSISTOR 审中-公开
    铟改进双极型晶体管

    公开(公告)号：EP1224693A2

    公开(公告)日：2002-07-24

    申请号：EP00970389.3

    申请日：2000-10-04

    申请人： Telefonaktiebolaget L M Ericsson (Publ)

    发明人： JOHANSSON, Ted ,  NORSTRÖM, Hans

    IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L29/73

    CPC分类号： H01L29/66287 ,  H01L21/26513 ,  H01L29/1004 ,  H01L29/167 ,  Y10S257/917

    摘要： A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price of high beta and high base resistance, separate boron and indium doping profiles are combined in the base. Thus, a transistor, which preserves most of the properties of pure boron-base transistor, is obtained, but with some parameters improved due to the added indium profile. This 'double-profile' or 'indium-enhanced' transistor exhibits improved beta-Early voltage product, reduced collector-base capacitance swing and lower temperature dependence of beta, but preserves the advantageous properties of a pure boron-base transistor. For this to work satisfactory, the indium profile must be contained within the boron profile in such a way that the beta and the effective base width are not significantly affected, otherwise the high frequency properties will be degraded. A typical process for fabricating a bipolar silicon high frequency NPN transistor together with some recorded parameters highlighting the benefits of an additional indium implant is presented.

    BIPOLARTRANSISTOR UND VERFAHREN ZU SEINER HERSTELLUNG
    13.
    发明公开
    BIPOLARTRANSISTOR UND VERFAHREN ZU SEINER HERSTELLUNG 有权

    公开(公告)号：EP1118124A1

    公开(公告)日：2001-07-25

    申请号：EP99955791.1

    申请日：1999-09-20

    申请人： Institut Für HalbleiterphysikFrankfurt (Oder) GmbH

    发明人： EHWALD, Karl-Ernst ,  TILLACK, Bernd ,  HEINEMANN, Bernd ,  KNOLL, Dieter ,  WOLANSKY, Dirk

    IPC分类号： H01L29/732 ,  H01L21/331

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide highly conductive connections between the metal contacts and the active (internal) transistor region and a minimized passive transistor surface while at the same time avoiding greater process complexity and increased contact resistances. To this end, by creating suitable epitaxis conditions a poly-silicon layer is deposited on the insulating area which is thicker than the epitaxis layer in the active transistor area. The greater thickness of the poly-silicon layer in relation to the epitaxis layer is achieved through the use of a very low temperature for the deposition of part or all of the buffer layer. Th use of a very low deposition temperature results in improved seeding of the insulating layer and a reduction in the deposition dead time, which makes it possible to produce a thicker layer on the insulating layer than in the active transistor area.

    摘要翻译： 本发明涉及一种双极晶体管及其制造方法。 本发明的目的是提供一种双极型晶体管及其制造方法，该双极型晶体管及其制造方法在使用具有差动外延的单工艺多晶硅技术来生产基座的过程中克服了传统系统的缺点，特别是进一步 为了改善双极晶体管的高速属性，在金属触点和有源（内部）晶体管区域之间提供高导电连接，并且提供最小化的无源晶体管表面，同时避免更大的工艺复杂性和增加的接触电阻。 为此，通过产生合适的外延条件，将多晶硅层沉积在比有源晶体管区域中的外延层更厚的绝缘区域上。 通过使用非常低的温度来沉积部分或全部缓冲层，实现多晶硅层相对于外延层的更大厚度。 使用非常低的沉积温度可以改善绝缘层的接种和减少沉积停滞时间，这使得可以在绝缘层上产生比有源晶体管区域更厚的层。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR
    14.
    发明公开
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 有权
    用于生产半导体组件与双极晶体管

    公开(公告)号：EP1048066A1

    公开(公告)日：2000-11-02

    申请号：EP99969180.1

    申请日：1999-08-31

    申请人： Koninklijke Philips Electronics N.V.

    发明人： TERPSTRA, Doede ,  EMONS, Catharina, H., H.

    IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737

    CPC分类号： H01L29/66287 ,  H01L29/66242

    摘要： The invention relates to the manufacture of a so-called differential bipolar transistor comprising a base (1A), an emitter (2) and a collector (3), the base (1A) being formed by applying a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body (10) where it forms the (monocrystalline) base (1A), and which semiconducting layer (1) borders, outside said monocrystalline part, on a non-monocrystalline part (4, 8) of the semiconductor body (10) where it forms a (non-monocrystalline) connecting region (1B) of the base (1A). In a method in accordance with the invention, the polycrystalline layer (4) is selectively provided on the electrically insulating region (8), in which process use is made of the mask (20) to form the electrically insulating region (8). This method is less laborious than the known method. In addition, the resultant transistors have excellent properties and their dimensions may be very small. Preferably, both in the manufacture of the insulating region (8), preferably an oxide-filled groove (8), and in the process of selectively applying the polycrystalline layer (4) to the insulating region, use is made of a deposition step followed by a chemico-mechanical polishing step.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR
    15.
    发明公开
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
    方法的半导体元件双极晶体管

    公开(公告)号：EP1048065A2

    公开(公告)日：2000-11-02

    申请号：EP99941512.8

    申请日：1999-08-03

    申请人： Koninklijke Philips Electronics N.V.

    发明人： EMONS, Catharina, H., H. ,  TERPSTRA, Doede ,  TIMMERING, Cornelis, E. ,  DE BOER, Wiebe, B.

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66287 ,  H01L21/223 ,  H01L21/2252 ,  H01L29/66242

    摘要： The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950 °C for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850 °C.

    High speed and low parasitic capacitance bipolar transistor and method for fabricating it
    16.
    发明公开
    High speed and low parasitic capacitance bipolar transistor and method for fabricating it 审中-公开
    高速和低寄生电容和它们的制备方法的双极晶体管

    公开(公告)号：EP0949665A2

    公开(公告)日：1999-10-13

    申请号：EP99106884.2

    申请日：1999-04-07

    申请人： NEC CORPORATION

    发明人： Sato, Fumihiko c/o NEC Corporation

    IPC分类号： H01L21/331 ,  H01L29/73 ,  H01L29/737

    CPC分类号： H01L29/66287 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7378

    摘要： A method for fabricating a semiconductor device including a bipolar transistor formed by epitaxial growth or ion implantation is provided. The bipolar transistor has an epitaxial silicon collector layer, a base region directly under an emitter defined as an intrinsic base and a peripheral region thereof defined as an outer base region. The method comprises the step of implanting ions into the collector layer to form a high concentration collector region at a location close to a buried region with using a photoresist used to form an aperture. The method further comprises the step of implanting ions into the collector layer to form a high concentration collector region directly beneath the base region after forming the base region.

    摘要翻译： 本发明提供一种用于半导体器件，包括由外延生长或离子注入形成的双极型晶体管的制造方法。 双极晶体管具有外延硅集电极层，其定义为对本征基和它们的定义为外基区的周边区域的发射极的正下方的底部区域。 该方法包括将离子注入所述集电极层在接近掩埋区与使用用于形成在孔光致抗蚀剂的位置，以形成高浓度的集电极区的步骤。 该方法还包括将离子注入所述集电极层在形成基极区域之后直接形成在基极区域下方的高浓度集电极区的步骤。

    Procédé de dépôt d'une région de silicium monocristallin
    17.
    发明公开
    Procédé de dépôt d'une région de silicium monocristallin 审中-公开
    Verfahren zur Abscheidung eines Gebietes aus monokristallinem Silizium

    公开(公告)号：EP0933801A1

    公开(公告)日：1999-08-04

    申请号：EP99410006.3

    申请日：1999-01-29

    申请人： STMicroelectronics S.A. ,  FRANCE TELECOM

    发明人： Gris, Yvon ,  Troillard, Germaine ,  Mourier, Jocelyne

    IPC分类号： H01L21/205 ,  H01L21/20 ,  C30B29/06 ,  C30B25/18 ,  H01L21/285 ,  H01L29/417 ,  H01L21/265

    CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66287 ,  Y10S117/913

    摘要： L'invention concerne un procédé de dépôt d'une couche de silicium sur un substrat de silicium monocristallin (11), de sorte que cette couche de silicium soit monocristalline, mais d'orientation différente de celle du substrat, comprenant les étapes consistant à délimiter une fenêtre sur le substrat ; créer à l'intérieur de la fenêtre des défauts interstitiels (14) dans une proportion atomique inférieure à un sur cent ; et effectuer un dépôt de silicium (15') dans des conditions correspondant généralement à celles d'un dépôt épitaxial, mais à une température inférieure à 900°C.

    摘要翻译： 在外延沉积条件下，但是在低温下将单晶硅层沉积到包含间隙缺陷的局部单晶硅衬底区域（14）上。 通过以下步骤进行单晶硅层沉积到不同取向的单晶硅衬底（11）上：（a）在衬底的暴露部分中产生小于1原子％的间隙缺陷（14）; 和（b）在外延沉积条件下沉积硅（15'），但低于900℃。优选特征：通过在氧化硅层中的开口注入电中性元素而产生缺陷。

    Verfahren zur Herstellung eines MOS-Transistors
    19.
    发明公开
    Verfahren zur Herstellung eines MOS-Transistors 失效
    Verfahren zur Herstellung采用MOS晶体管

    公开(公告)号：EP0809279A2

    公开(公告)日：1997-11-26

    申请号：EP97114782.2

    申请日：1992-08-19

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Klose, Helmut, Dr. ,  Meul, Hans-Willi, Dr. ,  Meister, Thomas, Dr. ,  Stengl, Reinhard, Dr.

    IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/331

    CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

    摘要： Auf einem Substrat (21) aus einkristallinem Halbleitermaterial wird eine erste Schicht (23) aus SiO 2 und eine zweite Schicht (24) aus polykristallinem Silizium erzeugt. Die erste Schicht (23) und die zweite Schicht (24) werden so strukturiert, daß eine Unterätzung (29) der ersten Schicht (23) unter die zweite Schicht (24) entsteht, in der die Oberfläche des Substrats (21) freigelegt wird. Mittels selektiver Epitaxie wird auf der freiliegenden Oberfläche des Substrats (21) ein einkristallines Gebiet (210) erzeugt, das als Kanalgebiet für einen MOS-Transistor verwendet wird.

    摘要翻译： MOS晶体管制造方法包括（a）在单晶硅衬底（21）上制造第一SiO 2层（23）和第二多晶硅层（24），第一层是可选择性蚀刻的。 第二层; （b）构造第一和第二层（23,24）以在单晶区域（210）中露出衬底表面; （c）用选择性外延期间在其表面没有成核的第三层（281）覆盖第二层（24）的表面和侧壁，并且抗蚀刻第一层（23）; （d）以选择性方式wrt进行各向同性蚀刻。 基板（21）和第二层（24），以在第二层（24）下方的蚀刻（29）下在第一层内露出基板表面; （e）通过在暴露的衬底表面上的选择性外延生产单晶区域（210）; （f）掺杂第二层（24）以在与用作沟道区的单晶区（210）相邻的第二层部分中形成源区和漏区（241,242）; 和（g）在单晶区域表面上产生栅极电介质，然后在与源极/漏极区域（241,242）绝缘的栅电极之间产生。