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公开(公告)号：EP2254300A1
公开(公告)日：2010-11-24
申请号：EP10176033.8
申请日：1998-01-06
CPC分类号： H04L27/2602 , H04L1/0002 , H04L5/1446 , H04L25/08 , H04L27/2605 , H04L27/2607 , H04L27/2647 , H04L27/2662
摘要： An OFDM system uses a normal mode which has a symbol length T, a guard time T G and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KT G where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.
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公开(公告)号：EP2248129A1
公开(公告)日：2010-11-10
申请号：EP09708151.7
申请日：2009-01-08
发明人： KIM, Jin-Ki
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
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公开(公告)号：EP2245633A2
公开(公告)日：2010-11-03
申请号：EP08871249.2
申请日：2008-12-15
发明人： KIM, Jin-Ki
IPC分类号： G11C16/06
CPC分类号： G06F12/0607 , G06F2212/1016 , G06F2212/1041 , G06F2212/1048 , G06F2212/2022
摘要： Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width.
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公开(公告)号：EP2242058A2
公开(公告)日：2010-10-20
申请号：EP10171414.5
申请日：2007-03-29
发明人： Kim, Jin-Ki
IPC分类号： G11C7/10 , G11C11/4193 , G11C16/00
CPC分类号： G11C7/1042 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C7/1021 , G11C16/10 , G11C16/32 , G11C2216/22 , G11C2216/24
摘要： There is disclosed a method for programming in a Flash memory system having a plurality Flash memory devices, the method comprising: receiving a data file having a plurality of pages; if all of the plurality of pages of the data file can fit into a single block of one of the plurality of Flash memory devices, programming all of the plurality of pages of the data file into the single block of the one of the plurality of Flash memory devices; otherwise, if all of the plurality of pages of the data file can fit into a plurality of blocks including one block in each of the plurality of memory devices, interleave programming all of the plurality of pages of the data file across the plurality of blocks including one block in each of the plurality of memory devices; and otherwise, interleave programming a subset of the plurality of pages of the data file into a plurality of blocks including one block in each of the plurality of memory devices and removing the subset of the plurality of pages of the data file from the data file.
摘要翻译： 公开了一种在具有多个闪速存储器件的闪速存储器系统中编程的方法，该方法包括：接收具有多页的数据文件; 如果数据文件的所有多页都可以装配到多个闪存设备之一的单个块中，则将数据文件的多个页面中的所有页面编程成多个闪存中的一个的单个块 存储设备; 否则，如果数据文件的所有多页都可以适应多个存储装置中的每一个中包括一个块的多个块，则跨多个块交织数据文件的所有多个页面，包括 在所述多个存储器件的每一个中的一个块; 否则，将数据文件的多个页面的子集编程成包括多个存储器件中的每一个中的一个块的多个块，并从数据文件中移除数据文件的多个页面的子集。
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公开(公告)号：EP2223301A1
公开(公告)日：2010-09-01
申请号：EP08800326.4
申请日：2008-09-15
发明人： OH, HakJune
IPC分类号： G11C11/413 , G11C11/4193 , G11C7/20
CPC分类号： G06F1/3203 , G06F1/3275 , G11C16/16 , G11C16/32 , Y02D10/14
摘要： A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.
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26.发明公开Telephone outlet with packet telephony adapter, and a network using same 有权Telefonanschluss mit Pakettelefonieadapter und ein Netz，welches selbigen verwendet
公开(公告)号：EP2222071A1
公开(公告)日：2010-08-25
申请号：EP10162261.1
申请日：2001-10-15
发明人： Binder, Yehuda
IPC分类号： H04M11/06 , H01R13/639
CPC分类号： H04M7/0081 , H04M1/2535 , H04M7/006
摘要： The present invention relates to a component for a data network. The component comprises a wiring connector connectable to wiring for connecting to the data network, a modem allowing for data communication over the wiring, a data connector connectable to a data terminal equipment unit, and a telephone connector connectable to a telephone unit for coupling an analog telephone signal to the telephone unit. The component further comprises an adapter which is connected to said telephone connector and operative to convert Voice over Internet Protocol (VoIP) packet telephony to the analog telephone signal, and a multi-port unit with a first port coupled to said data connector, a second port coupled to said modem and a third port coupled to said adapter, wherein said multi-port unit is operative to pass the VoIP packet telephony between said second and third ports. The adapter, the data connector, the telephone connector and the multi-port unit are included together within the single component.
摘要翻译： 本发明涉及数据网络的组件。 该组件包括可连接到数据网络的布线的接线连接器，允许通过布线进行数据通信的调制解调器，可连接到数据终端设备单元的数据连接器和可连接到电话单元的电话连接器，用于耦合模拟 电话信号到电话单元。 该组件还包括连接到所述电话连接器并且可操作以将语音互联网协议（VoIP）分组电话转换为模拟电话信号的适配器，以及具有耦合到所述数据连接器的第一端口的多端口单元，第二 耦合到所述调制解调器的端口和耦合到所述适配器的第三端口，其中所述多端口单元可操作以在所述第二端口和第三端口之间传递VoIP分组电话。 适配器，数据连接器，电话连接器和多端口单元都包含在单个组件中。
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公开(公告)号：EP1942561A3
公开(公告)日：2010-02-17
申请号：EP08000105.0
申请日：2004-11-11
发明人： Binder, Yehuda , Kobi, Rafael Gil , Hazani, Ami , Butbul, Shlomo
IPC分类号： H01R31/06 , H01R13/719 , H04B3/56
CPC分类号： H04B3/542 , H01R13/719 , H01R31/065 , H04B2203/5408
摘要： A device (250, 260) for coupling a data unit to a digital data signal in a service wiring system that comprises service wiring at least partially contained in wall of a building and a service outlet for connecting to the service wiring, the service wiring concurrently carrying service and digital data signals using frequency division multiplexing; the device comprising: a first service wiring connector (251, 261) having contacts that are directly connectable to the service wiring by engaging complementary contacts in the service outlet (42) without requiring disassembly or alteration of the service outlet (42), a first filter (252, 265) coupled to the first service wiring connector and operative to pass only the digital data signal, and a data connector (258) coupled to said first filter and connectable to a data unit; the service wiring is one out of telephone and CATV wirings and the service outlet is one out of telephone and CATV outlets, and the first service wiring connector (251, 261), the first filter (252, 265) and the data connector (258) are enclosed within a single enclosure having a mechanical attachment (41 a, 41 b) independent of the first service wiring connector (31) for mechanically securing the device to the service outlet (42), and wherein the first wiring service wiring connector is telephone or CATV connectors, and wherein the mechanical attachment is operative to attach the device to a front surface of the service outlet.
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公开(公告)号：EP2126917A1
公开(公告)日：2009-12-02
申请号：EP07845610.0
申请日：2007-11-29
发明人： KIM, Jin-Ki
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
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29.发明公开NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES 审中-公开具有多个外部电源不可非易失性半导体存储器
公开(公告)号：EP2122629A1
公开(公告)日：2009-11-25
申请号：EP08714579.3
申请日：2008-02-12
发明人： KIM, Jin-Ki , GILLINGHAM, Peter
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
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公开(公告)号：EP2122628A1
公开(公告)日：2009-11-25
申请号：EP08714555.3
申请日：2008-02-06
发明人： KIM, Jin-Ki , PYEON, Hong Beom
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.
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