公开(公告)号：EP0080058A2

公开(公告)日：1983-06-01

申请号：EP82109508.0

申请日：1982-10-14

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Chappell, Terry Ivan ,  Woodall, Jerry McPherson

IPC分类号： H01L29/205 ,  H01L29/267 ,  H01L29/80 ,  H01L29/72

CPC分类号： H01L29/66856 ,  H01L21/30635 ,  H01L29/1029 ,  H01L29/205 ,  H01L29/267 ,  H01L29/8122

摘要： An intermediate structure for use in the manufacture of semiconductor devices such as field effect transistors, comprises a monocrystalline semiconductor body having a first outer layer (2), a central layer (3) and a second outer layer (4) each of said first and second outer layers being of semiconductor material different from the semiconductor material of the central layer and forming a heterojunction (5, 6) whith the central layer. The thickness of the central layer (3) is of the order of the transport length of a charge carrier in the semiconductor material of that layer. Preferably, at least two adjacent layers of the intermediate structure have substantially equal electron energy work functions.
A vertical field effect transistor is formed (FIGS. 12 to 15) in a portion of an intermediate structure by removing areas (30, 31) of the second outer and central layers (4, 3) on each side of the portion, removing an area (32) of the second outer layer (4) at one end of the portion, etching the central layer (3) to form a web (22) connecting the first and second outer layers (2, 4), forming insulation (25, 27) on the exposed surfaces of the first and second outer layers (2, 4), forming a Schottky barrier electrode (23, 24) on the web and providing electrical contacts (35) to the first and second outer layers.

摘要翻译： 用于半导体器件的制造中使用的中间结构：如场效应晶体管，包括具有第一外层（2），中央层的单晶半导体主体（3）和第二外层（4），每个所述的第一和 第二外层与所述中心层的半导体材料不同的半导体材料制成，并且形成蒙山中心层的异质结（5，6）。 中心层（3）的厚度是电荷载体的传送长度的在没有层的半导体材料的数量级。 优选地，中间结构的至少两个相邻的层具有基本上相等的电子能量的功函数。 ... 一种垂直场效应晶体管中的中间结构的一部分通过去除区域第二外和中央层形成（30，31）（4,3）上的部分的每一侧上，除去在区域（ 32）在该部分的一端的第二外层（4），蚀刻所述中间层（3）以形成幅材（22）连接所述第一和第二外层（2，4）形成绝缘（25，27 ）所述第一和第二外层（2,4）的暴露表面，形成在网络上的肖特基势垒电极（23,24），并提供电触点（35）连接到第一和第二外层上。

公开(公告)号：EP0191544B1

公开(公告)日：1992-05-20

申请号：EP86300122.8

申请日：1986-01-09

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Rajeevakumar, Thekkemadathil Velayudan ,  Schuster, Stanley Everett ,  Terman, Lewis Madison

IPC分类号： G11C8/00

CPC分类号： G11C8/10

公开(公告)号：EP0244587B1

公开(公告)日：1991-11-13

申请号：EP87103205.8

申请日：1987-03-06

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Schuster, Stanley Everett

IPC分类号： H03K3/356 ,  G11C8/00

CPC分类号： H03K3/356113 ,  H03K3/356017

公开(公告)号：EP0330852A3

公开(公告)日：1991-03-27

申请号：EP89101781.6

申请日：1989-02-02

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Chappell, Terry Ivan ,  Schuster, Stanley Everett

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A φPC line is included for receiving a φPC precharge clock signal thereon and a φR line is provided for receiving a φR reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices (1-7) connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node (16) depending on the address bits state. The decoder/driver circuit further includes a selection means (8-11) having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node (17, 18) of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line (WLi) and is further responsive to the second selection signal to provide an output signal on a second memory word line (WLi+1).

公开(公告)号：EP0244587A3

公开(公告)日：1989-05-24

申请号：EP87103205.8

申请日：1987-03-06

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Schuster, Stanley Everett

IPC分类号： H03K3/356 ,  G11C8/00

CPC分类号： H03K3/356113 ,  H03K3/356017

摘要： A complementary input circuit is used to transfer the state of an external input (ADR IN) to the internal signal lines (ADR, ADR) of an integrated circuit chip. A nonlinear input circuit has an input terminal (ADR IN) for receiving the external input and provides an output to a first node (a) only when the external input exceeds a reference voltage (V R ) and a threshold voltage. It comprises further latch means having first and second output nodes (b. c) connected to the internal signal lines (ADR, ADR ) of the integrated circuit chip and having an input node common to said first node (a) for receiving the output of the nonlinear input circuit, said latch means comprising transistor devices (3, 4, 5. 6) which are partially cross-coupled.

公开(公告)号：EP0303811A1

公开(公告)日：1989-02-22

申请号：EP88110694.2

申请日：1988-07-05

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Chappell, Terry Ivan ,  Schuster, Stanley Everett

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/1039 ,  G11C7/12

摘要： A semiconductor random access memory chip wherein the cycle time is less than the access time for any combi­nation of read or write sequence. The semiconductor random access memory chip is partitioned into relative­ly small sub-arrays with local decoding (RS, WS) and precharg­ing (BLPC). The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

摘要翻译： 半导体随机存取存储器芯片，其中循环时间小于读或写顺序的任何组合的存取时间。 半导体随机存取存储器芯片被局部解码（RS，WS）和预充电（BLPC）分割成相对小的子阵列。 存储器芯片以流水线方式工作，在任何给定的时间内通过芯片传播多于一个的访问，并且其中周期时间受到子阵列周期的限制，其中周期时间小于具有周期时间的存储器芯片的访问时间 大于通过相同子阵列访问的访问时间。 存储器芯片还结合了动态存储技术，以实现非常快速的访问和预充电时间。

公开(公告)号：EP0080058B1

公开(公告)日：1988-06-01

申请号：EP82109508.0

申请日：1982-10-14

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Chappell, Terry Ivan ,  Woodall, Jerry McPherson

IPC分类号： H01L29/205 ,  H01L29/267 ,  H01L29/80 ,  H01L29/72

CPC分类号： H01L29/66856 ,  H01L21/30635 ,  H01L29/1029 ,  H01L29/205 ,  H01L29/267 ,  H01L29/8122

公开(公告)号：EP0181760A3

公开(公告)日：1987-08-26

申请号：EP85308022

申请日：1985-11-05

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Ning, Tak Hung ,  Terman, Lewis Madison

IPC分类号： H01L27/08 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L21/76889 ,  H01L21/823835 ,  H01L23/53271 ,  H01L27/0925 ,  H01L29/456 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

摘要： All the gates and source/drain contacts in a CMOS device (1) are formed from polysilicon or polycide. Using two levels of polysilicon or polycide, the first level is used to simultaneously form the gate (10) of one (2) of the CMOS transistors and buried contacts (30, 31) to the source/drain regions (13,14) of the other (3) CMOS transistor. The second level of polysilicon or polycide is then used to simultaneously form the gate (15) of the other (3) CMOS transistor and the buried contacts (28, 29) to the source/drain regions (8,9) of the first mentioned CMOS transistor. Because all the gates and contacts are polysilicon or polycide, it is possible to make interconnections between the gate on one of the devices and the source or drain of the other of the devices and between the gate on the other of the devices and the source/drain on said one of the devices simply by patterning the polysilicon or polycide layers.

摘要翻译： CMOS器件（1）中的所有栅极和源极/漏极触点由多晶硅或多晶硅形成。 使用两级多晶硅或多晶硅，第一级用于同时形成一个（2）CMOS晶体管的栅极（10）和埋入触点（30,31）到源极/漏极区域（13,14）的栅极 另一（3）个CMOS晶体管。 然后使用第二级多晶硅或多晶硅化物将另一（3）CMOS晶体管的栅极（15）和埋入触点（28,29）同时形成到第一提及的源极/漏极区域（8,9） CMOS晶体管。 因为所有的栅极和触点都是多晶硅或多晶硅，所以可以在器件之一的栅极和器件的另一个的源极或漏极之间以及另一个器件的栅极之间形成互连，并且源/ 通过图案化多晶硅或多晶硅化物层，在所述一个器件上的漏极。

公开(公告)号：EP0181760A2

公开(公告)日：1986-05-21

申请号：EP85308022.4

申请日：1985-11-05

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane ,  Ning, Tak Hung ,  Terman, Lewis Madison

IPC分类号： H01L27/08 ,  H01L23/52 ,  H01L21/82

CPC分类号： H01L21/76889 ,  H01L21/823835 ,  H01L23/53271 ,  H01L27/0925 ,  H01L29/456 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

摘要： All the gates and source/drain contacts in a CMOS device (1) are formed from polysilicon or polycide. Using two levels of polysilicon or polycide, the first level is used to simultaneously form the gate (10) of one (2) of the CMOS transistors and buried contacts (30, 31) to the source/drain regions (13,14) of the other (3) CMOS transistor. The second level of polysilicon or polycide is then used to simultaneously form the gate (15) of the other (3) CMOS transistor and the buried contacts (28, 29) to the source/drain regions (8,9) of the first mentioned CMOS transistor. Because all the gates and contacts are polysilicon or polycide, it is possible to make interconnections between the gate on one of the devices and the source or drain of the other of the devices and between the gate on the other of the devices and the source/drain on said one of the devices simply by patterning the polysilicon or polycide layers.

摘要翻译： CMOS器件（1）中的所有栅极和源极/漏极触点由多晶硅或多晶硅形成。 使用两级多晶硅或多晶硅，第一级用于同时形成一个（2）CMOS晶体管的栅极（10）和埋入触点（30,31）到源极/漏极区域（13,14）的栅极 另一（3）个CMOS晶体管。 然后使用第二级多晶硅或多晶硅化物将另一（3）CMOS晶体管的栅极（15）和埋入触点（28,29）同时形成到第一提及的源极/漏极区域（8,9） CMOS晶体管。 因为所有的栅极和触点都是多晶硅或多晶硅，所以可以在器件之一的栅极和器件的另一个的源极或漏极之间以及另一个器件的栅极之间形成互连，并且源/ 通过图案化多晶硅或多晶硅化物层，在所述一个器件上的漏极。

公开(公告)号：EP0166964A1

公开(公告)日：1986-01-08

申请号：EP85106583.9

申请日：1985-05-29

申请人： International Business Machines Corporation

发明人： Chappell, Barbara Alane

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L23/522 ,  H01L27/1112 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a double level polysilicon semiconductor structure, eg for a static RAM cell, a silicided outer region (42) of one portion (40) of the second level polysilicon layer serves as a conductive bus while an adjacent portion (34) serves as a resistor. The silicided outer region (42) is formed by depositing a silicide-forming metal on the one portion (40) of the second level polysilicon layer and annealing the structure. The second level polysilicon layer is undoped or only lightly doped.

摘要翻译： 在双级多晶硅半导体结构中，例如对于静态RAM单元，第二级多晶硅层的一部分（40）的硅化外区（42）用作导电总线，而相邻部分（34）用作电阻 。 硅化物外部区域（42）通过在第二层多晶硅层的一部分（40）上沉积硅化物形成金属并退火该结构而形成。 第二级多晶硅层未掺杂或仅轻掺杂。