公开(公告)号：EP1599881A1

公开(公告)日：2005-11-30

申请号：EP04708564.2

申请日：2004-02-05

申请人： SanDisk Corporation

发明人： LUTZE, Jeffrey, W. ,  CHEN, Jian ,  LI, Yan ,  HIGASHITANI, Masaaki

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

公开(公告)号：EP1543529A2

公开(公告)日：2005-06-22

申请号：EP03754785.8

申请日：2003-09-23

申请人： SanDisk Corporation

发明人： CERNEA, Raul-Adrian ,  LI, Yan

IPC分类号： G11C16/28 ,  G11C11/56 ,  G11C16/26

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/26

摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

公开(公告)号：EP1543521A1

公开(公告)日：2005-06-22

申请号：EP03770415.2

申请日：2003-09-18

申请人： SanDisk Corporation

发明人： CERNEA, Raul-Adrian ,  LI, Yan

IPC分类号： G11C7/06 ,  G11C16/26 ,  G11C11/56

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26

摘要： A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are controlled such that the voltage difference between each adjacent pair of lines is substantially independent of time while their conduction currents are being sensed. When this condition is imposed, all the alternate currents due to the various bit line capacitance drop out since they all depend on a time varying voltage difference. In another aspect, sensing the memory cell's conduction current is effected by noting its rate of discharging a dedicated capacitor provided in the sense amplifier.

公开(公告)号：EP1656676B1

公开(公告)日：2011-09-28

申请号：EP04777414.6

申请日：2004-06-30

申请人： SanDisk Corporation

发明人： CHEN, Jian ,  LUTZE, Jeffrey, W. ,  LI, Yan

IPC分类号： G11C11/56 ,  G11C16/34

CPC分类号： G11C16/3463 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

公开(公告)号：EP2335244A1

公开(公告)日：2011-06-22

申请号：EP09740220.0

申请日：2009-10-07

申请人： Sandisk Corporation

发明人： LI, Yan ,  FONG, Yupin, Kawing ,  CHAN, Siu Lung

IPC分类号： G11C11/56

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

公开(公告)号：EP2304734A1

公开(公告)日：2011-04-06

申请号：EP09774324.9

申请日：2009-06-30

申请人： Sandisk Corporation

发明人： LUTZE, Jeffrey, W. ,  LI, Yan

IPC分类号： G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

摘要： A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other type of control line) but not in the subset.

公开(公告)号：EP2074627B1

公开(公告)日：2010-09-15

申请号：EP07864477.0

申请日：2007-11-15

申请人： Sandisk Corporation

发明人： LI, Yan ,  KAMEI, Teruhiko ,  LUTZE, Jeffrey W.

IPC分类号： G11C16/12 ,  G11C11/56 ,  G06F11/10

CPC分类号： G06F11/1072 ,  G06F11/1068 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non¬ volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non¬ volatile storage elements that are not properly programmed.

公开(公告)号：EP1946324B1

公开(公告)日：2010-06-16

申请号：EP06816668.5

申请日：2006-10-11

申请人： SanDisk Corporation

发明人： LUTZE, Jeffrey, W. ,  LI, Yan ,  CHAN, Siu, L.

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

公开(公告)号：EP2186094A2

公开(公告)日：2010-05-19

申请号：EP08830722.8

申请日：2008-08-20

申请人： Sandisk Corporation

发明人： LI, Yan ,  FONG, Yupin, Kawing ,  MOKHLESI, Nima

IPC分类号： G11C7/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5647

摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

公开(公告)号：EP1671332B1

公开(公告)日：2009-06-10

申请号：EP04783607.7

申请日：2004-09-08

申请人： SanDisk Corporation

发明人： CERNEA, Raul-Adrian ,  LI, Yan ,  MOFIDI, Mehrdad ,  KHALID, Shahzad

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468

摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.