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161 条记录 (耗时 0.018 秒)

    Semiconductor memory with a sequence of clocked access codes for test mode entry
    22.
    发明授权
    Semiconductor memory with a sequence of clocked access codes for test mode entry 失效
    用的时钟控制的接入码的序列的半导体存储器进入测试模式

    公开(公告)号：EP0471544B1

    公开(公告)日：1997-05-14

    申请号：EP91307426.6

    申请日：1991-08-12

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Slemmer, William Carl ,  Coker, Thomas Allyn ,  McClure, David Charles

    IPC分类号： G06F11/26 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/46 ,  G01R31/31701 ,  G01R31/31719 ,  G11C7/1045

    摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

    HOST-DEVICE INTERFACE FOR DEBUG AUTHENTICATION
    24.
    发明公开
    HOST-DEVICE INTERFACE FOR DEBUG AUTHENTICATION 审中-实审

    公开(公告)号：EP4379582A1

    公开(公告)日：2024-06-05

    申请号：EP23210739.1

    申请日：2023-11-17

    申请人： STMicroelectronics International N.V.

    发明人： CHBANI, Xavier ,  VAN-DEN-BOSSCHE, Nadia

    IPC分类号： G06F21/44 ,  G01R31/317 ,  G06F11/36

    CPC分类号： G01R31/31719 ,  G06F11/3656 ,  G06F21/445 ,  G01R31/31705

    摘要： The present disclosure relates to an electronic device comprising: a debug port (112) providing a communications interface for debugging purposes; one or more processing unit access ports (AP1, APn); an authentication interface circuit (110) configured to authenticate the external device (200); and a further access port (APO) coupled between the debug port (112) and the authentication interface circuit (110), the further access port (APO) being configured to be in an open state in which communications are relayed between the debug port and the authentication interface circuit (110), the authentication interface circuit (110) comprising registers (202) including a status register (302) capable of being read by the external device (200) via the debug port (112) and the further access port (APO), the status register being configured to store an indication of the open or closed state of each of the processing unit access ports (AP1, APn) .

    METHOD OF TESTING THE RESISTANCE OF A CIRCUIT TO A SIDE CHANNEL ANALYSIS
    26.
    发明公开
    METHOD OF TESTING THE RESISTANCE OF A CIRCUIT TO A SIDE CHANNEL ANALYSIS 审中-公开
    一种电路测试电阻对侧信道分析的方法

    公开(公告)号：EP3220306A1

    公开(公告)日：2017-09-20

    申请号：EP17156293.7

    申请日：2017-02-15

    申请人： ESHARD

    发明人： WURCKER, Antoine ,  THIEBEAULD DE LA CROUEE, Hugues ,  CLAVIER, Christophe

    IPC分类号： G06F21/55 ,  H04L9/00 ,  G01R31/317 ,  G09C1/00

    CPC分类号： H04L9/003 ,  G01R31/31719 ,  G06F21/72 ,  G06F21/75 ,  G09C1/00 ,  H04L9/002 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3249 ,  H04L9/3252 ,  H04L2209/12

    摘要： The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets (CH) by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value resulting from the application of a second surjective function, merging according to a selected merging scheme, cumulative occurrence numbers in the cumulative occurrence number sets (HT), and analyzing the merged cumulative occurrence number sets (HTR1) to determine the part of the secret data.

    摘要翻译： 本发明涉及一种电路的测试方法，包括：当该电路执行应用的一组不同密码操作的操作时，获取包括与待测试电路的活动相关联的物理量的值的多个值集合 对于每个值集合，为每个值集合选择至少第一子集，通过处理单元对通过应用于值集合的第一子集的值的第一全映射函数变换的值的出现次数进行计数， 形成针对操作集合的每个操作设置的值集合的出现编号以及部分秘密数据的每个可能值，计算部分操作结果，通过添加事件来计算累积出现编号集合（CH） 对应于操作集合的操作的数字集合，其在应用于秘密数据的该部分的可能值的相同值或等同值时提供一个pa （HTTR）中的累计出现次数，并且分析合并的累积出现次数集合（HTR1），并且根据所选择的合并方案来合并具有相同的变换值， 确定秘密数据的一部分。

    Enabling secured debug of an integrated circuit
    28.
    发明授权
    Enabling secured debug of an integrated circuit 有权
    启用安全故障的集成电路

    公开(公告)号：EP2843429B1

    公开(公告)日：2016-11-23

    申请号：EP13182739.6

    申请日：2013-09-03

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Svensson, Peter

    IPC分类号： G01R31/3185 ,  G01R31/317

    CPC分类号： F16K25/04 ,  B01J8/0015 ,  B01J2208/00548 ,  B01J2208/00787 ,  F16K3/02 ,  F16K27/044 ,  G01R31/31719 ,  G01R31/318588

    摘要： The disclosed invention enables secured debug of an integrated circuit (300) which has a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit (340), a test interface (312) through which the test operation mode is controllable, an on-chip memory (350) which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources (360, 364, 370) which are inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive (401) an authenticated object (401) through the test interface, and store (401) the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure (362) to determine (501) that the authenticated object is available in the on-chip memory, authenticate (502) the authenticated object, and - upon successful authentication - render (503a, 503b) the more protected resources accessible to a debug host (310) external to the integrated circuit.

    Integrated circuit with distributed clock tampering detectors
    29.
    发明公开
    Integrated circuit with distributed clock tampering detectors 审中-公开
    Integrierte Schaltung mit verteilten Taktmanipulationsdetektoren

    公开(公告)号：EP2983102A1

    公开(公告)日：2016-02-10

    申请号：EP14180234.8

    申请日：2014-08-07

    申请人： EM Microelectronic-Marin SA

    发明人： Walter, Fabrice

    IPC分类号： G06F21/55 ,  G06F21/75

    CPC分类号： G01R31/31727 ,  G01R31/31719 ,  G06F21/554 ,  G06F21/75 ,  H03K19/003

    摘要： A circuit configuration for secure application includes several internal frequency detectors (10) arranged in digital units at critical points of an integrated circuit (30). The clock detectors (10) are concealed in the digital part of the integrated circuit (30) each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors (10) are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

    摘要翻译： 用于安全应用的电路配置包括在集成电路（30）的关键点处以数字单元布置的几个内部频率检测器（10）。 时钟检测器（10）被隐藏在集成电路（30）的数字部分中，每个作为标准单元（触发器单元），以防止任何外部操作并且隐藏其功能。 时钟检测器（10）优选地设置在时钟树拓扑中，时钟树拓扑可以处于几个级别，用于在临界点通过不同的数字单元树分发时钟信号。 如果在任何级别监视了外部时钟攻击，则通过时钟检测器网络生成报警。

    Enabling secured debug of an integrated circuit
    30.
    发明公开
    Enabling secured debug of an integrated circuit 有权
    Ermöglichungder sicherenStörungsbeseitigungeiner integrierten Schaltung

    公开(公告)号：EP2843429A1

    公开(公告)日：2015-03-04

    申请号：EP13182739.6

    申请日：2013-09-03

    申请人： Telefonaktiebolaget L M Ericsson (Publ)

    发明人： Svensson, Peter

    IPC分类号： G01R31/3185 ,  G01R31/317

    CPC分类号： F16K25/04 ,  B01J8/0015 ,  B01J2208/00548 ,  B01J2208/00787 ,  F16K3/02 ,  F16K27/044 ,  G01R31/31719 ,  G01R31/318588

    摘要： The disclosed invention enables secured debug of an integrated circuit (300) which has a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit (340), a test interface (312) through which the test operation mode is controllable, an on-chip memory (350) which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources (360, 364, 370) which are inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive (401) an authenticated object (401) through the test interface, and store (401) the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure (362) to determine (501) that the authenticated object is available in the on-chip memory, authenticate (502) the authenticated object, and - upon successful authentication - render (503a, 503b) the more protected resources accessible to a debug host (310) external to the integrated circuit.

    摘要翻译： 所公开的发明使得具有测试操作模式和安全任务操作模式的集成电路（300）的安全调试。 集成电路具有处理单元（340），测试操作模式可控制的测试接口（312），可在测试操作模式和安全任务操作模式下访问的片上存储器（350） 以及在测试操作模式中不可访问的一个或多个受保护资源（360,364,370）。 处理单元在测试操作模式下被配置为通过测试接口接收认证对象（401）（401），并将接收到的认证对象存储（401）到片上存储器中。 此外，处理单元还被配置为在重新设置为安全任务操作模式时，执行引导过程（362）以确定（501）已验证对象在片上存储器中可用，认证（502）已认证对象， 以及 - 在成功认证之后，渲染（503a，503b）对集成电路外部的调试主机（310）可访问的更多受保护的资源。